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drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none of these workarounds are actually tied to MTL as a platform; they only relate to the Xe_LPG graphics IP, regardless of what platform it appears in. At the moment MTL is the only platform that uses Xe_LPG with IP versions 12.70 and 12.71, but we can't count on this being true in the future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead that is purely based on IP version. IS_GFX_GT_IP_STEP() is also GT-based rather than device-based, which will help prevent mistakes where we accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+ media GT and vice-versa. v2: - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be used for both graphics and media IP (and any other kind of GTs that show up in the future). v3: - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani) - Move macro to intel_gt.h. (Andi) v4: - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and IS_GRAPHICS_STEP building blocks and name the parameters from/until rather than begin/fixed. (Jani) - Fix usage examples in comment. v5: - Tweak comment on macro. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-15-matthew.d.roper@intel.com
1 parent f7696de commit 5a21308

10 files changed

Lines changed: 62 additions & 43 deletions

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‎drivers/gpu/drm/i915/display/skl_universal_plane.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "skl_scaler.h"
2121
#include "skl_universal_plane.h"
2222
#include "skl_watermark.h"
23+
#include "gt/intel_gt.h"
2324
#include "pxp/intel_pxp.h"
2425

2526
static const u32 skl_plane_formats[] = {
@@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
21692170
enum pipe pipe, enum plane_id plane_id)
21702171
{
21712172
/* Wa_14017240301 */
2172-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2173-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
2173+
if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
2174+
IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
21742175
return false;
21752176

21762177
/* Wa_22011186057 */

‎drivers/gpu/drm/i915/gt/gen8_engine_cs.c‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@
44
*/
55

66
#include "gen8_engine_cs.h"
7-
#include "i915_drv.h"
87
#include "intel_engine_regs.h"
98
#include "intel_gpu_commands.h"
9+
#include "intel_gt.h"
1010
#include "intel_lrc.h"
1111
#include "intel_ring.h"
1212

@@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
226226
static int mtl_dummy_pipe_control(struct i915_request *rq)
227227
{
228228
/* Wa_14016712196 */
229-
if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
230-
IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
229+
if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
230+
IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
231231
u32 *cs;
232232

233233
/* dummy PIPE_CONTROL + depth flush */
@@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
799799
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
800800
{
801801
struct drm_i915_private *i915 = rq->i915;
802+
struct intel_gt *gt = rq->engine->gt;
802803
u32 flags = (PIPE_CONTROL_CS_STALL |
803804
PIPE_CONTROL_TLB_INVALIDATE |
804805
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
809810
PIPE_CONTROL_FLUSH_ENABLE);
810811

811812
/* Wa_14016712196 */
812-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
813-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
813+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
814+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
814815
/* dummy PIPE_CONTROL + depth flush */
815816
cs = gen12_emit_pipe_control(cs, 0,
816817
PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);

‎drivers/gpu/drm/i915/gt/intel_gt.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,26 @@ struct drm_printer;
2525
GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
2626
GRAPHICS_VER_FULL((gt)->i915) <= (until)))
2727

28+
/*
29+
* Check that the GT is a graphics GT with a specific IP version and has
30+
* a stepping in the range [from, until). The lower stepping bound is
31+
* inclusive, the upper bound is exclusive. The most common use-case of this
32+
* macro is for checking bounds for workarounds, which usually have a stepping
33+
* ("from") at which the hardware issue is first present and another stepping
34+
* ("until") at which a hardware fix is present and the software workaround is
35+
* no longer necessary. E.g.,
36+
*
37+
* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)
38+
* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
39+
*
40+
* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
41+
* stepping bound for the specified IP version.
42+
*/
43+
#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \
44+
BUILD_BUG_ON_ZERO((until) <= (from)) + \
45+
(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
46+
IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
47+
2848
#define GT_TRACE(gt, fmt, ...) do { \
2949
const struct intel_gt *gt__ __maybe_unused = (gt); \
3050
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \

‎drivers/gpu/drm/i915/gt/intel_gt_mcr.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,7 @@
33
* Copyright © 2022 Intel Corporation
44
*/
55

6-
#include "i915_drv.h"
7-
6+
#include "intel_gt.h"
87
#include "intel_gt_mcr.h"
98
#include "intel_gt_print.h"
109
#include "intel_gt_regs.h"
@@ -166,8 +165,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
166165
gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
167166
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
168167
/* Wa_14016747170 */
169-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
170-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
168+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
169+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
171170
fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
172171
intel_uncore_read(gt->uncore,
173172
MTL_GT_ACTIVITY_FACTOR));

‎drivers/gpu/drm/i915/gt/intel_lrc.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1346,8 +1346,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
13461346
cs = gen12_emit_aux_table_inv(ce->engine, cs);
13471347

13481348
/* Wa_16014892111 */
1349-
if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
1350-
IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
1349+
if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
1350+
IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
13511351
IS_DG2(ce->engine->i915))
13521352
cs = dg2_emit_draw_watermark_setting(cs);
13531353

‎drivers/gpu/drm/i915/gt/intel_reset.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
16411641
if (GRAPHICS_VER(gt->i915) < 11)
16421642
return false;
16431643

1644-
if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
1644+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
16451645
return true;
16461646

16471647
if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))

‎drivers/gpu/drm/i915/gt/intel_workarounds.c‎

Lines changed: 25 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -781,24 +781,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
781781
static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
782782
struct i915_wa_list *wal)
783783
{
784-
struct drm_i915_private *i915 = engine->i915;
784+
struct intel_gt *gt = engine->gt;
785785

786786
dg2_ctx_gt_tuning_init(engine, wal);
787787

788-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
789-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
788+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
789+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
790790
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
791791
}
792792

793793
static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
794794
struct i915_wa_list *wal)
795795
{
796-
struct drm_i915_private *i915 = engine->i915;
796+
struct intel_gt *gt = engine->gt;
797797

798798
xelpg_ctx_gt_tuning_init(engine, wal);
799799

800-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
801-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
800+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
801+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
802802
/* Wa_14014947963 */
803803
wa_masked_field_set(wal, VF_PREEMPTION,
804804
PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1640,8 +1640,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
16401640
/* Wa_22016670082 */
16411641
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
16421642

1643-
if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
1644-
IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
1643+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
1644+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
16451645
/* Wa_14014830051 */
16461646
wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
16471647

@@ -2293,23 +2293,24 @@ static void
22932293
rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
22942294
{
22952295
struct drm_i915_private *i915 = engine->i915;
2296+
struct intel_gt *gt = engine->gt;
22962297

2297-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2298-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
2298+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2299+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
22992300
/* Wa_22014600077 */
23002301
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
23012302
ENABLE_EU_COUNT_FOR_TDL_FLUSH);
23022303
}
23032304

2304-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2305-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2305+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2306+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
23062307
IS_DG2(i915)) {
23072308
/* Wa_1509727124 */
23082309
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
23092310
SC_DISABLE_POWER_OPTIMIZATION_EBB);
23102311
}
23112312

2312-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2313+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
23132314
IS_DG2(i915)) {
23142315
/* Wa_22012856258 */
23152316
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
@@ -2825,8 +2826,9 @@ static void
28252826
general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
28262827
{
28272828
struct drm_i915_private *i915 = engine->i915;
2829+
struct intel_gt *gt = engine->gt;
28282830

2829-
add_render_compute_tuning_settings(engine->gt, wal);
2831+
add_render_compute_tuning_settings(gt, wal);
28302832

28312833
if (GRAPHICS_VER(i915) >= 11) {
28322834
/* This is not a Wa (although referred to as
@@ -2847,27 +2849,27 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
28472849
GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
28482850
}
28492851

2850-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
2851-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
2852+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
2853+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
28522854
/* Wa_14017856879 */
28532855
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
28542856

2855-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2856-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
2857+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2858+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
28572859
/*
28582860
* Wa_14017066071
28592861
* Wa_14017654203
28602862
*/
28612863
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
28622864
MTL_DISABLE_SAMPLER_SC_OOO);
28632865

2864-
if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
2866+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
28652867
/* Wa_22015279794 */
28662868
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
28672869
DISABLE_PREFETCH_INTO_IC);
28682870

2869-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2870-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2871+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2872+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
28712873
IS_DG2(i915)) {
28722874
/* Wa_22013037850 */
28732875
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
@@ -2877,8 +2879,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
28772879
wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
28782880
}
28792881

2880-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2881-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2882+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2883+
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
28822884
IS_PONTEVECCHIO(i915) ||
28832885
IS_DG2(i915)) {
28842886
/* Wa_22014226127 */

‎drivers/gpu/drm/i915/gt/uc/intel_guc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
273273
flags |= GUC_WA_POLLCS;
274274

275275
/* Wa_14014475959 */
276-
if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
276+
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
277277
IS_DG2(gt->i915))
278278
flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
279279

‎drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
42654265

42664266
/* Wa_14014475959:dg2 */
42674267
if (engine->class == COMPUTE_CLASS)
4268-
if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
4268+
if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
42694269
IS_DG2(engine->i915))
42704270
engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
42714271

‎drivers/gpu/drm/i915/i915_drv.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -686,10 +686,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
686686
#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
687687
(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
688688

689-
#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
690-
(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
691-
IS_GRAPHICS_STEP(__i915, since, until))
692-
693689
#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
694690
(IS_METEORLAKE(__i915) && \
695691
IS_DISPLAY_STEP(__i915, since, until))

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