Skip to content

Commit 5acb925

Browse files
krzkDinh Nguyen
krzk
authored and
Dinh Nguyen
committed
arm64: dts: altera: Use lowercase hex
The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
1 parent 1cb8486 commit 5acb925

6 files changed

Lines changed: 31 additions & 31 deletions

File tree

‎arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -382,7 +382,7 @@
382382

383383
pinctrl0: pinctrl@ffd13000 {
384384
compatible = "pinctrl-single";
385-
reg = <0xffd13000 0xA0>;
385+
reg = <0xffd13000 0xa0>;
386386
#pinctrl-cells = <1>;
387387
pinctrl-single,register-width = <32>;
388388
pinctrl-single,function-mask = <0x0000000f>;

‎arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@
192192

193193
root: partition@4200000 {
194194
label = "Root Filesystem - UBIFS";
195-
reg = <0x04200000 0x0BE00000>;
195+
reg = <0x04200000 0x0be00000>;
196196
};
197197
};
198198
};

‎arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -174,12 +174,12 @@
174174

175175
qspi_boot: partition@0 {
176176
label = "Boot and fpga data";
177-
reg = <0x0 0x03FE0000>;
177+
reg = <0x0 0x03fe0000>;
178178
};
179179

180180
qspi_rootfs: partition@3fe0000 {
181181
label = "Root Filesystem - JFFS2";
182-
reg = <0x03FE0000 0x0C020000>;
182+
reg = <0x03fe0000 0x0c020000>;
183183
};
184184
};
185185
};

‎arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -622,31 +622,31 @@
622622
snps,dcb-algorithm;
623623
};
624624
queue1 {
625-
snps,weight = <0x0A>;
625+
snps,weight = <0x0a>;
626626
snps,dcb-algorithm;
627627
};
628628
queue2 {
629-
snps,weight = <0x0B>;
629+
snps,weight = <0x0b>;
630630
snps,coe-unsupported;
631631
snps,dcb-algorithm;
632632
};
633633
queue3 {
634-
snps,weight = <0x0C>;
634+
snps,weight = <0x0c>;
635635
snps,coe-unsupported;
636636
snps,dcb-algorithm;
637637
};
638638
queue4 {
639-
snps,weight = <0x0D>;
639+
snps,weight = <0x0d>;
640640
snps,coe-unsupported;
641641
snps,dcb-algorithm;
642642
};
643643
queue5 {
644-
snps,weight = <0x0E>;
644+
snps,weight = <0x0e>;
645645
snps,coe-unsupported;
646646
snps,dcb-algorithm;
647647
};
648648
queue6 {
649-
snps,weight = <0x0F>;
649+
snps,weight = <0x0f>;
650650
snps,coe-unsupported;
651651
snps,dcb-algorithm;
652652
};
@@ -735,31 +735,31 @@
735735
snps,dcb-algorithm;
736736
};
737737
queue1 {
738-
snps,weight = <0x0A>;
738+
snps,weight = <0x0a>;
739739
snps,dcb-algorithm;
740740
};
741741
queue2 {
742-
snps,weight = <0x0B>;
742+
snps,weight = <0x0b>;
743743
snps,coe-unsupported;
744744
snps,dcb-algorithm;
745745
};
746746
queue3 {
747-
snps,weight = <0x0C>;
747+
snps,weight = <0x0c>;
748748
snps,coe-unsupported;
749749
snps,dcb-algorithm;
750750
};
751751
queue4 {
752-
snps,weight = <0x0D>;
752+
snps,weight = <0x0d>;
753753
snps,coe-unsupported;
754754
snps,dcb-algorithm;
755755
};
756756
queue5 {
757-
snps,weight = <0x0E>;
757+
snps,weight = <0x0e>;
758758
snps,coe-unsupported;
759759
snps,dcb-algorithm;
760760
};
761761
queue6 {
762-
snps,weight = <0x0F>;
762+
snps,weight = <0x0f>;
763763
snps,coe-unsupported;
764764
snps,dcb-algorithm;
765765
};
@@ -848,31 +848,31 @@
848848
snps,dcb-algorithm;
849849
};
850850
queue1 {
851-
snps,weight = <0x0A>;
851+
snps,weight = <0x0a>;
852852
snps,dcb-algorithm;
853853
};
854854
queue2 {
855-
snps,weight = <0x0B>;
855+
snps,weight = <0x0b>;
856856
snps,coe-unsupported;
857857
snps,dcb-algorithm;
858858
};
859859
queue3 {
860-
snps,weight = <0x0C>;
860+
snps,weight = <0x0c>;
861861
snps,coe-unsupported;
862862
snps,dcb-algorithm;
863863
};
864864
queue4 {
865-
snps,weight = <0x0D>;
865+
snps,weight = <0x0d>;
866866
snps,coe-unsupported;
867867
snps,dcb-algorithm;
868868
};
869869
queue5 {
870-
snps,weight = <0x0E>;
870+
snps,weight = <0x0e>;
871871
snps,coe-unsupported;
872872
snps,dcb-algorithm;
873873
};
874874
queue6 {
875-
snps,weight = <0x0F>;
875+
snps,weight = <0x0f>;
876876
snps,coe-unsupported;
877877
snps,dcb-algorithm;
878878
};
@@ -918,24 +918,24 @@
918918

919919
pmu0_tbu3: pmu@160a2000 {
920920
compatible = "arm,smmu-v3-pmcg";
921-
reg = <0x160A2000 0x1000>,
922-
<0x160B2000 0x1000>;
921+
reg = <0x160a2000 0x1000>,
922+
<0x160b2000 0x1000>;
923923
interrupt-parent = <&intc>;
924924
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
925925
};
926926

927927
pmu0_tbu4: pmu@160c2000 {
928928
compatible = "arm,smmu-v3-pmcg";
929-
reg = <0x160C2000 0x1000>,
930-
<0x160D2000 0x1000>;
929+
reg = <0x160c2000 0x1000>,
930+
<0x160d2000 0x1000>;
931931
interrupt-parent = <&intc>;
932932
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
933933
};
934934

935935
pmu0_tbu5: pmu@160e2000 {
936936
compatible = "arm,smmu-v3-pmcg";
937-
reg = <0x160E2000 0x1000>,
938-
<0x160F2000 0x1000>;
937+
reg = <0x160e2000 0x1000>,
938+
<0x160f2000 0x1000>;
939939
interrupt-parent = <&intc>;
940940
interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
941941
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131

132132
root: partition@4200000 {
133133
label = "Root Filesystem - UBIFS";
134-
reg = <0x04200000 0x0BE00000>;
134+
reg = <0x04200000 0x0be00000>;
135135
};
136136
};
137137
};

‎arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -103,12 +103,12 @@
103103

104104
qspi_boot: partition@0 {
105105
label = "Boot and fpga data";
106-
reg = <0x0 0x03FE0000>;
106+
reg = <0x0 0x03fe0000>;
107107
};
108108

109109
qspi_rootfs: partition@3fe0000 {
110110
label = "Root Filesystem - JFFS2";
111-
reg = <0x03FE0000 0x0C020000>;
111+
reg = <0x03fe0000 0x0c020000>;
112112
};
113113
};
114114
};

0 commit comments

Comments
 (0)