Skip to content

Commit 5b70764

Browse files
IcenowyConchuOD
authored andcommitted
riscv: dts: starfive: add Orange Pi RV
Orange Pi RV is a SBC based on the StarFive VisionFive 2 board. Orange Pi RV features: - StarFive JH7110 SoC - GbE port connected to JH7110 GMAC0 via YT8531 PHY - 4x USB ports via VL805 PCIe USB controller connected to JH7110 pcie0 - M.2 M-key slot connected to JH7110 pcie1 - HDMI video output - 3.5mm audio output - Ampak AP6256 SDIO Wi-Fi/Bluetooth module on mmc0 - microSD slot on mmc1 - SPI NOR flash memory - 24c02 EEPROM (read only by default) Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: E Shattow <e@freeshell.de> [conor: amend comment to say what's missing] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
1 parent d94ebab commit 5b70764

2 files changed

Lines changed: 77 additions & 0 deletions

File tree

arch/riscv/boot/dts/starfive/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-deepcomputing-fml13v01.dtb
1212
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
1313
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
1414
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
15+
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-orangepi-rv.dtb
1516
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
1617
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
1718
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2+
/*
3+
* Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me>
4+
*/
5+
6+
/dts-v1/;
7+
#include "jh7110-common.dtsi"
8+
9+
/ {
10+
model = "Xunlong Orange Pi RV";
11+
compatible = "xunlong,orangepi-rv", "starfive,jh7110";
12+
13+
/* This regulator is always on by hardware */
14+
reg_vcc3v3_pcie: regulator-vcc3v3-pcie {
15+
compatible = "regulator-fixed";
16+
regulator-name = "vcc3v3-pcie";
17+
regulator-min-microvolt = <3300000>;
18+
regulator-max-microvolt = <3300000>;
19+
regulator-always-on;
20+
};
21+
22+
wifi_pwrseq: wifi-pwrseq {
23+
compatible = "mmc-pwrseq-simple";
24+
reset-gpios = <&sysgpio 62 GPIO_ACTIVE_LOW>;
25+
};
26+
};
27+
28+
&gmac0 {
29+
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
30+
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
31+
starfive,tx-use-rgmii-clk;
32+
status = "okay";
33+
};
34+
35+
&mmc0 {
36+
#address-cells = <1>;
37+
#size-cells = <0>;
38+
cap-sd-highspeed;
39+
mmc-pwrseq = <&wifi_pwrseq>;
40+
vmmc-supply = <&reg_vcc3v3_pcie>;
41+
vqmmc-supply = <&vcc_3v3>;
42+
status = "okay";
43+
44+
ap6256: wifi@1 {
45+
compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
46+
reg = <1>;
47+
/* TODO: out-of-band IRQ on GPIO21, lacking pinctrl support */
48+
};
49+
};
50+
51+
&mmc1 {
52+
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
53+
};
54+
55+
&pcie0 {
56+
status = "okay";
57+
};
58+
59+
&pcie1 {
60+
status = "okay";
61+
};
62+
63+
&phy0 {
64+
rx-internal-delay-ps = <1500>;
65+
tx-internal-delay-ps = <1500>;
66+
motorcomm,rx-clk-drv-microamp = <3970>;
67+
motorcomm,rx-data-drv-microamp = <2910>;
68+
motorcomm,tx-clk-adj-enabled;
69+
motorcomm,tx-clk-10-inverted;
70+
motorcomm,tx-clk-100-inverted;
71+
motorcomm,tx-clk-1000-inverted;
72+
};
73+
74+
&pwmdac {
75+
status = "okay";
76+
};

0 commit comments

Comments
 (0)