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Ben Skeggsairlied
Ben Skeggs
authored and
airlied
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drm/nouveau/mmu/r535: initial support
- Valid VRAM regions are read from GSP-RM, and used to construct our MM - BAR1/BAR2 VMMs modified to be shared with RM - Client VMMs have RM VASPACE objects created for them - Adds FBSR to backup system objects in VRAM across suspend Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-37-skeggsb@gmail.com
1 parent 830531e commit 5bf0257

33 files changed

Lines changed: 1201 additions & 4 deletions

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‎drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h‎

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@@ -11,6 +11,10 @@ struct nvkm_bar {
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spinlock_t lock;
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bool bar2;
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14+
void __iomem *flushBAR2PhysMode;
15+
struct nvkm_memory *flushFBZero;
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void __iomem *flushBAR2;
17+
1418
/* whether the BAR supports to be ioremapped WC or should be uncached */
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bool iomap_uncached;
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};

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h‎

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@@ -65,6 +65,13 @@ struct nvkm_gsp {
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} heap;
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u64 addr;
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u64 size;
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struct {
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u64 addr;
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u64 size;
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} region[16];
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int region_nr;
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u32 rsvd_size;
6875
} fb;
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7077
struct {
@@ -159,6 +166,11 @@ struct nvkm_gsp {
159166
} intr[32];
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int intr_nr;
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struct {
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u64 rm_bar1_pdb;
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u64 rm_bar2_pdb;
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} bar;
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162174
const struct nvkm_gsp_rm {
163175
void *(*rpc_get)(struct nvkm_gsp *, u32 fn, u32 argc);
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void *(*rpc_push)(struct nvkm_gsp *, void *argv, bool wait, u32 repc);

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h‎

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@@ -24,6 +24,11 @@ struct nvkm_instmem {
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struct nvkm_ramht *ramht;
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struct nvkm_memory *ramro;
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struct nvkm_memory *ramfc;
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struct {
29+
struct sg_table fbsr;
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bool fbsr_valid;
31+
} rm;
2732
};
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u32 nvkm_instmem_rd32(struct nvkm_instmem *, u32 addr);

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h‎

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@@ -2,6 +2,7 @@
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#ifndef __NVKM_MMU_H__
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#define __NVKM_MMU_H__
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#include <core/subdev.h>
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#include <subdev/gsp.h>
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struct nvkm_vma {
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struct list_head head;
@@ -63,6 +64,16 @@ struct nvkm_vmm {
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void *nullp;
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bool replay;
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struct {
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u64 bar2_pdb;
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struct nvkm_gsp_client client;
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struct nvkm_gsp_device device;
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struct nvkm_gsp_object object;
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struct nvkm_vma *rsvd;
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} rm;
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};
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int nvkm_vmm_new(struct nvkm_device *, u64 addr, u64 size, void *argv, u32 argc,

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl84a0.h‎

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#ifndef __src_common_sdk_nvidia_inc_class_cl84a0_h__
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#define __src_common_sdk_nvidia_inc_class_cl84a0_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#define NV01_MEMORY_LIST_SYSTEM (0x00000081)
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#define NV01_MEMORY_LIST_FBMEM (0x00000082)
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#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl90f1.h‎

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#ifndef __src_common_sdk_nvidia_inc_class_cl90f1_h__
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#define __src_common_sdk_nvidia_inc_class_cl90f1_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#define FERMI_VASPACE_A (0x000090f1)
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#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h‎

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@@ -59,4 +59,26 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
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NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
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} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
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typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
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NvU32 fbsrType;
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NvU32 numRegions;
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NvHandle hClient;
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NvHandle hSysMem;
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NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
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NvBool bEnteringGcoffState;
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} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
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typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
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NvU32 fbsrType;
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NvHandle hClient;
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NvHandle hVidMem;
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NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
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NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
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NV_DECLARE_ALIGNED(NvU64 size, 8);
82+
} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
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#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl90f1.h‎

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#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
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#define __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8+
* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
12+
* to deal in the Software without restriction, including without limitation
13+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
14+
* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
16+
*
17+
* The above copyright notice and this permission notice shall be included in
18+
* all copies or substantial portions of the Software.
19+
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26+
* DEALINGS IN THE SOFTWARE.
27+
*/
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#define GMMU_FMT_MAX_LEVELS 6U
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#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */
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typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
34+
/*!
35+
* [in] GPU sub-device handle - this API only supports unicast.
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* Pass 0 to use subDeviceId instead.
37+
*/
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NvHandle hSubDevice;
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/*!
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* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
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*/
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NvU32 subDeviceId;
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/*!
46+
* [in] Page size (VA coverage) of the level to reserve.
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* This need not be a leaf (page table) page size - it can be
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* the coverage of an arbitrary level (including root page directory).
49+
*/
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NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
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/*!
53+
* [in] First GPU virtual address of the range to reserve.
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* This must be aligned to pageSize.
55+
*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
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/*!
59+
* [in] Last GPU virtual address of the range to reserve.
60+
* This (+1) must be aligned to pageSize.
61+
*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
63+
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/*!
65+
* [in] Number of PDE levels to copy.
66+
*/
67+
NvU32 numLevelsToCopy;
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/*!
70+
* [in] Per-level information.
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*/
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struct {
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/*!
74+
* Physical address of this page level instance.
75+
*/
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NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
77+
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/*!
79+
* Size in bytes allocated for this level instance.
80+
*/
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NV_DECLARE_ALIGNED(NvU64 size, 8);
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/*!
84+
* Aperture in which this page level instance resides.
85+
*/
86+
NvU32 aperture;
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/*!
89+
* Page shift corresponding to the level
90+
*/
91+
NvU8 pageShift;
92+
} levels[GMMU_FMT_MAX_LEVELS];
93+
} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
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#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h‎

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#ifndef __src_common_sdk_nvidia_inc_nvos_h__
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#define __src_common_sdk_nvidia_inc_nvos_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
5+
6+
/*
7+
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8+
* SPDX-License-Identifier: MIT
9+
*
10+
* Permission is hereby granted, free of charge, to any person obtaining a
11+
* copy of this software and associated documentation files (the "Software"),
12+
* to deal in the Software without restriction, including without limitation
13+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
14+
* and/or sell copies of the Software, and to permit persons to whom the
15+
* Software is furnished to do so, subject to the following conditions:
16+
*
17+
* The above copyright notice and this permission notice shall be included in
18+
* all copies or substantial portions of the Software.
19+
*
20+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26+
* DEALINGS IN THE SOFTWARE.
27+
*/
28+
29+
#define NVOS02_FLAGS_PHYSICALITY 7:4
30+
#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000)
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#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001)
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#define NVOS02_FLAGS_LOCATION 11:8
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#define NVOS02_FLAGS_LOCATION_PCI (0x00000000)
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#define NVOS02_FLAGS_LOCATION_AGP (0x00000001)
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#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002)
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#define NVOS02_FLAGS_COHERENCY 15:12
37+
#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000)
38+
#define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001)
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#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002)
40+
#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003)
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#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004)
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#define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005)
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#define NVOS02_FLAGS_ALLOC 17:16
44+
#define NVOS02_FLAGS_ALLOC_NONE (0x00000001)
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#define NVOS02_FLAGS_GPU_CACHEABLE 18:18
46+
#define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000)
47+
#define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001)
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#define NVOS02_FLAGS_KERNEL_MAPPING 19:19
50+
#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000)
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#define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001)
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#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20
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#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000)
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#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001)
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#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21
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#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000)
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#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001)
59+
60+
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22
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#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000)
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#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001)
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#define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23
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#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000)
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#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001)
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#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24
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#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001)
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#define NVOS02_FLAGS_MEMORY_PROTECTION 26:25
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#define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000)
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#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001)
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#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002)
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#define NVOS02_FLAGS_MAPPING 31:30
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#define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000)
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#define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001)
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#define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002)
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typedef struct
82+
{
83+
NvU32 index;
84+
NvV32 flags;
85+
NvU64 vaSize NV_ALIGN_BYTES(8);
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NvU64 vaStartInternal NV_ALIGN_BYTES(8);
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NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
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NvU32 bigPageSize;
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NvU64 vaBase NV_ALIGN_BYTES(8);
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} NV_VASPACE_ALLOCATION_PARAMETERS;
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#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default
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#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/generated/g_fbsr_nvoc.h‎

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#ifndef __src_nvidia_generated_g_fbsr_nvoc_h__
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#define __src_nvidia_generated_g_fbsr_nvoc_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
5+
6+
/*
7+
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8+
* SPDX-License-Identifier: MIT
9+
*
10+
* Permission is hereby granted, free of charge, to any person obtaining a
11+
* copy of this software and associated documentation files (the "Software"),
12+
* to deal in the Software without restriction, including without limitation
13+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
14+
* and/or sell copies of the Software, and to permit persons to whom the
15+
* Software is furnished to do so, subject to the following conditions:
16+
*
17+
* The above copyright notice and this permission notice shall be included in
18+
* all copies or substantial portions of the Software.
19+
*
20+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#define FBSR_TYPE_DMA 4 // Copy using DMA. Fastest.
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#endif

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