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ivecerakuba-moo
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dpll: zl3073x: Fix output pin phase adjustment sign
The output pin phase adjustment functions incorrectly negate the phase compensation value. Per the ZL3073x datasheet, the output phase compensation register is simply a signed two's complement integer where: - Positive values move the phase later in time - Negative values move the phase earlier in time No negation is required. The erroneous negation caused phase adjustments to be applied in the wrong direction. Note that input pin phase adjustment correctly uses negation because the hardware has an inverted convention for input references (positive moves phase earlier, negative moves phase later). Fixes: 6287262 ("dpll: zl3073x: Add support to adjust phase") Signed-off-by: Ivan Vecera <ivecera@redhat.com> Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Link: https://patch.msgid.link/20260205181055.129768-1-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Lines changed: 4 additions & 8 deletions

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drivers/dpll/zl3073x/dpll.c

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1039,10 +1039,8 @@ zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
10391039
out_id = zl3073x_output_pin_out_get(pin->id);
10401040
out = zl3073x_out_state_get(zldev, out_id);
10411041

1042-
/* Convert value to ps and reverse two's complement negation applied
1043-
* during 'set'
1044-
*/
1045-
*phase_adjust = -out->phase_comp * pin->phase_gran;
1042+
/* The value in the register is expressed in half synth clock cycles. */
1043+
*phase_adjust = out->phase_comp * pin->phase_gran;
10461044

10471045
return 0;
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}
@@ -1064,10 +1062,8 @@ zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
10641062
out_id = zl3073x_output_pin_out_get(pin->id);
10651063
out = *zl3073x_out_state_get(zldev, out_id);
10661064

1067-
/* The value in the register is stored as two's complement negation
1068-
* of requested value and expressed in half synth clock cycles.
1069-
*/
1070-
out.phase_comp = -phase_adjust / pin->phase_gran;
1065+
/* The value in the register is expressed in half synth clock cycles. */
1066+
out.phase_comp = phase_adjust / pin->phase_gran;
10711067

10721068
/* Update output configuration from mailbox */
10731069
return zl3073x_out_state_set(zldev, out_id, &out);

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