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Merge tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into clk-starfive
Pull Starfive clk driver updates from Conor Dooley: - Initial JH7110 clk/reset support A rake of patches, initially worked on by Emil & later picked up by Hal that add support for the sys/aon clock & reset controllers on StarFive's JH7110 SoC. This SoC is largely similar to the existing JH7100, so a bunch of refactoring is done to share as many bits as possible between the two. What's here (plus the already applied pinctrl bits) should be sufficient to boot a basic initramfs. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: generalise StarFive clk/reset entries reset: starfive: Add StarFive JH7110 reset driver clk: starfive: Add StarFive JH7110 always-on clock driver clk: starfive: Add StarFive JH7110 system clock driver reset: starfive: jh71x0: Use 32bit I/O on 32bit registers reset: starfive: Rename "jh7100" to "jh71x0" for the common code reset: starfive: Extract the common JH71X0 reset code reset: starfive: Factor out common JH71X0 reset code reset: Create subdirectory for StarFive drivers reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE clk: starfive: Rename "jh7100" to "jh71x0" for the common code clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h clk: starfive: Factor out common JH7100 and JH7110 code clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2 parents eeac8ed + 63a30e1 commit 601e5d4

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‎Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Always-On Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-aoncrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference or GMAC0 RGMII RX
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- description: STG AXI/AHB
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- description: APB Bus
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- description: GMAC0 GTX
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference or GMAC0 RGMII RX
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- description: STG AXI/AHB or GMAC0 RGMII RX
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- description: APB Bus or STG AXI/AHB
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- description: GMAC0 GTX or APB Bus
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- description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference
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- description: GMAC0 RGMII RX
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- description: STG AXI/AHB
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- description: APB Bus
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- description: GMAC0 GTX
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- description: RTC Oscillator (32.768 kHz)
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clock-names:
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oneOf:
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- minItems: 5
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items:
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- const: osc
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- enum:
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- gmac0_rmii_refin
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- gmac0_rgmii_rxin
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- const: stg_axiahb
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- const: apb_bus
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- const: gmac0_gtxclk
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- const: rtc_osc
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- minItems: 6
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items:
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- const: osc
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- const: gmac0_rmii_refin
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- const: gmac0_rgmii_rxin
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- const: stg_axiahb
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- const: apb_bus
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- const: gmac0_gtxclk
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- const: rtc_osc
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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clock-controller@17000000 {
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compatible = "starfive,jh7110-aoncrg";
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reg = <0x17000000 0x10000>;
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clocks = <&osc>, <&gmac0_rmii_refin>,
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<&gmac0_rgmii_rxin>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_APB_BUS>,
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<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
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<&rtc_osc>;
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clock-names = "osc", "gmac0_rmii_refin",
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"gmac0_rgmii_rxin", "stg_axiahb",
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"apb_bus", "gmac0_gtxclk",
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"rtc_osc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-syscrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference or GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference
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- description: GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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clock-names:
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oneOf:
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- items:
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- const: osc
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- enum:
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- gmac1_rmii_refin
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- gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- items:
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- const: osc
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- const: gmac1_rmii_refin
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- const: gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@13020000 {
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compatible = "starfive,jh7110-syscrg";
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reg = <0x13020000 0x10000>;
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clocks = <&osc>, <&gmac1_rmii_refin>,
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎MAINTAINERS‎

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S: Maintained
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F: arch/riscv/boot/dts/starfive/
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19910-
STARFIVE JH7100 CLOCK DRIVERS
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M: Emil Renner Berthing <kernel@esmil.dk>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
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F: drivers/clk/starfive/clk-starfive-jh7100*
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F: include/dt-bindings/clock/starfive-jh7100*.h
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STARFIVE JH7110 MMC/SD/SDIO DRIVER
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M: William Qiu <william.qiu@starfivetech.com>
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S: Supported
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F: Documentation/devicetree/bindings/mmc/starfive*
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F: drivers/mmc/host/dw_mmc-starfive.c
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19916+
STARFIVE JH71X0 CLOCK DRIVERS
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M: Emil Renner Berthing <kernel@esmil.dk>
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M: Hal Feng <hal.feng@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
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F: drivers/clk/starfive/clk-starfive-jh71*
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F: include/dt-bindings/clock/starfive?jh71*.h
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STARFIVE JH71X0 PINCTRL DRIVERS
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M: Emil Renner Berthing <kernel@esmil.dk>
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M: Jianlong Huang <jianlong.huang@starfivetech.com>
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F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
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F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
1993219933

19933-
STARFIVE JH7100 RESET CONTROLLER DRIVER
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STARFIVE JH71X0 RESET CONTROLLER DRIVERS
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M: Emil Renner Berthing <kernel@esmil.dk>
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M: Hal Feng <hal.feng@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
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F: drivers/reset/reset-starfive-jh7100.c
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F: include/dt-bindings/reset/starfive-jh7100.h
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F: drivers/reset/starfive/reset-starfive-jh71*
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F: include/dt-bindings/reset/starfive?jh71*.h
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1994019942
STARFIVE JH71XX PMU CONTROLLER DRIVER
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M: Walker Chen <walker.chen@starfivetech.com>

‎drivers/clk/Makefile‎

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obj-y += sprd/
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obj-$(CONFIG_ARCH_STI) += st/
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obj-$(CONFIG_ARCH_STM32) += stm32/
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obj-$(CONFIG_SOC_STARFIVE) += starfive/
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obj-y += starfive/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-y += sunxi-ng/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/

‎drivers/clk/starfive/Kconfig‎

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# SPDX-License-Identifier: GPL-2.0
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config CLK_STARFIVE_JH71X0
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bool
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config CLK_STARFIVE_JH7100
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bool "StarFive JH7100 clock support"
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depends on SOC_STARFIVE || COMPILE_TEST
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default SOC_STARFIVE
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depends on ARCH_STARFIVE || COMPILE_TEST
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select CLK_STARFIVE_JH71X0
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default ARCH_STARFIVE
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help
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Say yes here to support the clock controller on the StarFive JH7100
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SoC.
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config CLK_STARFIVE_JH7100_AUDIO
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tristate "StarFive JH7100 audio clock support"
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depends on CLK_STARFIVE_JH7100
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default m if SOC_STARFIVE
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select CLK_STARFIVE_JH71X0
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default m if ARCH_STARFIVE
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help
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Say Y or M here to support the audio clocks on the StarFive JH7100
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SoC.
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config CLK_STARFIVE_JH7110_SYS
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bool "StarFive JH7110 system clock support"
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depends on ARCH_STARFIVE || COMPILE_TEST
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select AUXILIARY_BUS
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select CLK_STARFIVE_JH71X0
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select RESET_STARFIVE_JH7110
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default ARCH_STARFIVE
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help
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Say yes here to support the system clock controller on the
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StarFive JH7110 SoC.
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config CLK_STARFIVE_JH7110_AON
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tristate "StarFive JH7110 always-on clock support"
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depends on CLK_STARFIVE_JH7110_SYS
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select AUXILIARY_BUS
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select CLK_STARFIVE_JH71X0
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select RESET_STARFIVE_JH7110
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default m if ARCH_STARFIVE
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help
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Say yes here to support the always-on clock controller on the
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StarFive JH7110 SoC.

‎drivers/clk/starfive/Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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# StarFive Clock
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obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
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obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
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obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o

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