@@ -721,7 +721,7 @@ bool ath10k_pci_irq_pending(struct ath10k *ar)
721721 return false;
722722}
723723
724- void ath10k_pci_disable_and_clear_legacy_irq (struct ath10k * ar )
724+ void ath10k_pci_disable_and_clear_intx_irq (struct ath10k * ar )
725725{
726726 /* IMPORTANT: INTR_CLR register has to be set after
727727 * INTR_ENABLE is set to 0, otherwise interrupt can not be
@@ -739,7 +739,7 @@ void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
739739 PCIE_INTR_ENABLE_ADDRESS );
740740}
741741
742- void ath10k_pci_enable_legacy_irq (struct ath10k * ar )
742+ void ath10k_pci_enable_intx_irq (struct ath10k * ar )
743743{
744744 ath10k_pci_write32 (ar , SOC_CORE_BASE_ADDRESS +
745745 PCIE_INTR_ENABLE_ADDRESS ,
@@ -1935,7 +1935,7 @@ static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
19351935static void ath10k_pci_irq_disable (struct ath10k * ar )
19361936{
19371937 ath10k_ce_disable_interrupts (ar );
1938- ath10k_pci_disable_and_clear_legacy_irq (ar );
1938+ ath10k_pci_disable_and_clear_intx_irq (ar );
19391939 ath10k_pci_irq_msi_fw_mask (ar );
19401940}
19411941
@@ -1949,7 +1949,7 @@ static void ath10k_pci_irq_sync(struct ath10k *ar)
19491949static void ath10k_pci_irq_enable (struct ath10k * ar )
19501950{
19511951 ath10k_ce_enable_interrupts (ar );
1952- ath10k_pci_enable_legacy_irq (ar );
1952+ ath10k_pci_enable_intx_irq (ar );
19531953 ath10k_pci_irq_msi_fw_unmask (ar );
19541954}
19551955
@@ -3111,11 +3111,11 @@ static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
31113111 return IRQ_NONE ;
31123112 }
31133113
3114- if ((ar_pci -> oper_irq_mode == ATH10K_PCI_IRQ_LEGACY ) &&
3114+ if ((ar_pci -> oper_irq_mode == ATH10K_PCI_IRQ_INTX ) &&
31153115 !ath10k_pci_irq_pending (ar ))
31163116 return IRQ_NONE ;
31173117
3118- ath10k_pci_disable_and_clear_legacy_irq (ar );
3118+ ath10k_pci_disable_and_clear_intx_irq (ar );
31193119 ath10k_pci_irq_msi_fw_mask (ar );
31203120 napi_schedule (& ar -> napi );
31213121
@@ -3152,7 +3152,7 @@ static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
31523152 napi_schedule (ctx );
31533153 goto out ;
31543154 }
3155- ath10k_pci_enable_legacy_irq (ar );
3155+ ath10k_pci_enable_intx_irq (ar );
31563156 ath10k_pci_irq_msi_fw_unmask (ar );
31573157 }
31583158
@@ -3177,7 +3177,7 @@ static int ath10k_pci_request_irq_msi(struct ath10k *ar)
31773177 return 0 ;
31783178}
31793179
3180- static int ath10k_pci_request_irq_legacy (struct ath10k * ar )
3180+ static int ath10k_pci_request_irq_intx (struct ath10k * ar )
31813181{
31823182 struct ath10k_pci * ar_pci = ath10k_pci_priv (ar );
31833183 int ret ;
@@ -3199,8 +3199,8 @@ static int ath10k_pci_request_irq(struct ath10k *ar)
31993199 struct ath10k_pci * ar_pci = ath10k_pci_priv (ar );
32003200
32013201 switch (ar_pci -> oper_irq_mode ) {
3202- case ATH10K_PCI_IRQ_LEGACY :
3203- return ath10k_pci_request_irq_legacy (ar );
3202+ case ATH10K_PCI_IRQ_INTX :
3203+ return ath10k_pci_request_irq_intx (ar );
32043204 case ATH10K_PCI_IRQ_MSI :
32053205 return ath10k_pci_request_irq_msi (ar );
32063206 default :
@@ -3232,7 +3232,7 @@ static int ath10k_pci_init_irq(struct ath10k *ar)
32323232 ath10k_pci_irq_mode );
32333233
32343234 /* Try MSI */
3235- if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY ) {
3235+ if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_INTX ) {
32363236 ar_pci -> oper_irq_mode = ATH10K_PCI_IRQ_MSI ;
32373237 ret = pci_enable_msi (ar_pci -> pdev );
32383238 if (ret == 0 )
@@ -3250,15 +3250,15 @@ static int ath10k_pci_init_irq(struct ath10k *ar)
32503250 * For now, fix the race by repeating the write in below
32513251 * synchronization checking.
32523252 */
3253- ar_pci -> oper_irq_mode = ATH10K_PCI_IRQ_LEGACY ;
3253+ ar_pci -> oper_irq_mode = ATH10K_PCI_IRQ_INTX ;
32543254
32553255 ath10k_pci_write32 (ar , SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS ,
32563256 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL );
32573257
32583258 return 0 ;
32593259}
32603260
3261- static void ath10k_pci_deinit_irq_legacy (struct ath10k * ar )
3261+ static void ath10k_pci_deinit_irq_intx (struct ath10k * ar )
32623262{
32633263 ath10k_pci_write32 (ar , SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS ,
32643264 0 );
@@ -3269,8 +3269,8 @@ static int ath10k_pci_deinit_irq(struct ath10k *ar)
32693269 struct ath10k_pci * ar_pci = ath10k_pci_priv (ar );
32703270
32713271 switch (ar_pci -> oper_irq_mode ) {
3272- case ATH10K_PCI_IRQ_LEGACY :
3273- ath10k_pci_deinit_irq_legacy (ar );
3272+ case ATH10K_PCI_IRQ_INTX :
3273+ ath10k_pci_deinit_irq_intx (ar );
32743274 break ;
32753275 default :
32763276 pci_disable_msi (ar_pci -> pdev );
@@ -3307,14 +3307,14 @@ int ath10k_pci_wait_for_target_init(struct ath10k *ar)
33073307 if (val & FW_IND_INITIALIZED )
33083308 break ;
33093309
3310- if (ar_pci -> oper_irq_mode == ATH10K_PCI_IRQ_LEGACY )
3310+ if (ar_pci -> oper_irq_mode == ATH10K_PCI_IRQ_INTX )
33113311 /* Fix potential race by repeating CORE_BASE writes */
3312- ath10k_pci_enable_legacy_irq (ar );
3312+ ath10k_pci_enable_intx_irq (ar );
33133313
33143314 mdelay (10 );
33153315 } while (time_before (jiffies , timeout ));
33163316
3317- ath10k_pci_disable_and_clear_legacy_irq (ar );
3317+ ath10k_pci_disable_and_clear_intx_irq (ar );
33183318 ath10k_pci_irq_msi_fw_mask (ar );
33193319
33203320 if (val == 0xffffffff ) {
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