|
248 | 248 | #define bPAEnd 0xf |
249 | 249 | #define bTREnd 0x0f000000 |
250 | 250 | #define bRFEnd 0x000f0000 |
251 | | -/* T2R */ |
252 | | -#define bCCAMask 0x000000f0 |
253 | | -#define bR2RCCAMask 0x00000f00 |
254 | | -#define bHSSI_R2TDelay 0xf8000000 |
255 | | -#define bHSSI_T2RDelay 0xf80000 |
256 | 251 | /* Channel gain at continue TX. */ |
257 | | -#define bContTxHSSI 0x400 |
258 | | -#define bIGFromCCK 0x200 |
259 | | -#define bAGCAddress 0x3f |
260 | | -#define bRxHPTx 0x7000 |
261 | | -#define bRxHPT2R 0x38000 |
262 | | -#define bRxHPCCKIni 0xc0000 |
263 | | -#define bAGCTxCode 0xc00000 |
264 | | -#define bAGCRxCode 0x300000 |
265 | 252 | #define b3WireDataLength 0x800 |
266 | 253 | #define b3WireAddressLength 0x400 |
267 | | -#define b3WireRFPowerDown 0x1 |
268 | | -/*#define bHWSISelect 0x8 */ |
269 | | -#define b2GPAPEPolarity 0x80000000 |
270 | | -#define bRFSW_TxDefaultAnt 0x3 |
271 | | -#define bRFSW_TxOptionAnt 0x30 |
272 | | -#define bRFSW_RxDefaultAnt 0x300 |
273 | | -#define bRFSW_RxOptionAnt 0x3000 |
274 | | -#define bRFSI_3WireData 0x1 |
275 | | -#define bRFSI_3WireClock 0x2 |
276 | | -#define bRFSI_3WireLoad 0x4 |
277 | | -#define bRFSI_3WireRW 0x8 |
278 | 254 | /* 3-wire total control */ |
279 | | -#define bRFSI_3Wire 0xf |
280 | 255 | #define bRFSI_RFENV 0x10 |
281 | | -#define bRFSI_TRSW 0x20 |
282 | | -#define bRFSI_TRSWB 0x40 |
283 | | -#define bRFSI_ANTSW 0x100 |
284 | | -#define bRFSI_ANTSWB 0x200 |
285 | | -#define bRFSI_PAPE 0x400 |
286 | | -#define bBandSelect 0x1 |
287 | | -#define bHTSIG2_GI 0x80 |
288 | | -#define bHTSIG2_Smoothing 0x01 |
289 | | -#define bHTSIG2_Sounding 0x02 |
290 | | -#define bHTSIG2_Aggreaton 0x08 |
291 | | -#define bHTSIG2_STBC 0x30 |
292 | | -#define bHTSIG2_AdvCoding 0x40 |
293 | | -#define bHTSIG2_NumOfHTLTF 0x300 |
294 | | -#define bHTSIG2_CRC8 0x3fc |
295 | | -#define bHTSIG1_MCS 0x7f |
296 | | -#define bHTSIG1_BandWidth 0x80 |
297 | | -#define bHTSIG1_HTLength 0xffff |
298 | | -#define bLSIG_Rate 0xf |
299 | | -#define bLSIG_Reserved 0x10 |
300 | | -#define bLSIG_Length 0x1fffe |
301 | | -#define bLSIG_Parity 0x20 |
302 | | -#define bCCKRxPhase 0x4 |
303 | 256 | #define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */ |
304 | 257 | #define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */ |
305 | 258 | #define bLSSIReadBackData 0xfff |
306 | | -#define bLSSIReadOKFlag 0x1000 |
307 | | -#define bCCKSampleRate 0x8 /* 0: 44 MHz, 1: 88MHz */ |
308 | | - |
309 | | -#define bRegulator0Standby 0x1 |
310 | | -#define bRegulatorPLLStandby 0x2 |
311 | | -#define bRegulator1Standby 0x4 |
312 | | -#define bPLLPowerUp 0x8 |
313 | | -#define bDPLLPowerUp 0x10 |
314 | | -#define bDA10PowerUp 0x20 |
315 | | -#define bAD7PowerUp 0x200 |
316 | | -#define bDA6PowerUp 0x2000 |
317 | | -#define bXtalPowerUp 0x4000 |
318 | | -#define b40MDClkPowerUP 0x8000 |
319 | | -#define bDA6DebugMode 0x20000 |
| 259 | + |
320 | 260 | #define bDA6Swing 0x380000 |
321 | 261 | #define bADClkPhase 0x4000000 |
322 | 262 | #define b80MClkDelay 0x18000000 |
|
0 commit comments