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Linus Walleij
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Merge tag 'intel-pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.19-1 * Add and use common macro INTEL_GPP() to avoid duplication * Export intel_gpio_add_pin_ranges() and reuse it instead of custom copies * Unify error messages with help of dev_err_probe() Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 parents ebd6148 + 8daf70e commit 6156424

19 files changed

Lines changed: 319 additions & 451 deletions

‎drivers/pinctrl/intel/pinctrl-alderlake.c‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,6 @@
2727
#define ADL_S_GPI_IS 0x200
2828
#define ADL_S_GPI_IE 0x220
2929

30-
#define ADL_GPP(r, s, e, g) \
31-
{ \
32-
.reg_num = (r), \
33-
.base = (s), \
34-
.size = ((e) - (s) + 1), \
35-
.gpio_base = (g), \
36-
}
37-
3830
#define ADL_N_COMMUNITY(b, s, e, g) \
3931
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
4032

@@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = {
316308
};
317309

318310
static const struct intel_padgroup adln_community0_gpps[] = {
319-
ADL_GPP(0, 0, 25, 0), /* GPP_B */
320-
ADL_GPP(1, 26, 41, 32), /* GPP_T */
321-
ADL_GPP(2, 42, 66, 64), /* GPP_A */
311+
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
312+
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
313+
INTEL_GPP(2, 42, 66, 64), /* GPP_A */
322314
};
323315

324316
static const struct intel_padgroup adln_community1_gpps[] = {
325-
ADL_GPP(0, 67, 74, 96), /* GPP_S */
326-
ADL_GPP(1, 75, 94, 128), /* GPP_I */
327-
ADL_GPP(2, 95, 118, 160), /* GPP_H */
328-
ADL_GPP(3, 119, 139, 192), /* GPP_D */
329-
ADL_GPP(4, 140, 168, 224), /* vGPIO */
317+
INTEL_GPP(0, 67, 74, 96), /* GPP_S */
318+
INTEL_GPP(1, 75, 94, 128), /* GPP_I */
319+
INTEL_GPP(2, 95, 118, 160), /* GPP_H */
320+
INTEL_GPP(3, 119, 139, 192), /* GPP_D */
321+
INTEL_GPP(4, 140, 168, 224), /* vGPIO */
330322
};
331323

332324
static const struct intel_padgroup adln_community4_gpps[] = {
333-
ADL_GPP(0, 169, 192, 256), /* GPP_C */
334-
ADL_GPP(1, 193, 217, 288), /* GPP_F */
335-
ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
336-
ADL_GPP(3, 224, 248, 320), /* GPP_E */
325+
INTEL_GPP(0, 169, 192, 256), /* GPP_C */
326+
INTEL_GPP(1, 193, 217, 288), /* GPP_F */
327+
INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
328+
INTEL_GPP(3, 224, 248, 320), /* GPP_E */
337329
};
338330

339331
static const struct intel_padgroup adln_community5_gpps[] = {
340-
ADL_GPP(0, 249, 256, 352), /* GPP_R */
332+
INTEL_GPP(0, 249, 256, 352), /* GPP_R */
341333
};
342334

343335
static const struct intel_community adln_communities[] = {
@@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = {
680672
};
681673

682674
static const struct intel_padgroup adls_community0_gpps[] = {
683-
ADL_GPP(0, 0, 24, 0), /* GPP_I */
684-
ADL_GPP(1, 25, 47, 32), /* GPP_R */
685-
ADL_GPP(2, 48, 59, 64), /* GPP_J */
686-
ADL_GPP(3, 60, 86, 96), /* vGPIO */
687-
ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */
675+
INTEL_GPP(0, 0, 24, 0), /* GPP_I */
676+
INTEL_GPP(1, 25, 47, 32), /* GPP_R */
677+
INTEL_GPP(2, 48, 59, 64), /* GPP_J */
678+
INTEL_GPP(3, 60, 86, 96), /* vGPIO */
679+
INTEL_GPP(4, 87, 94, 128), /* vGPIO_0 */
688680
};
689681

690682
static const struct intel_padgroup adls_community1_gpps[] = {
691-
ADL_GPP(0, 95, 118, 160), /* GPP_B */
692-
ADL_GPP(1, 119, 126, 192), /* GPP_G */
693-
ADL_GPP(2, 127, 150, 224), /* GPP_H */
683+
INTEL_GPP(0, 95, 118, 160), /* GPP_B */
684+
INTEL_GPP(1, 119, 126, 192), /* GPP_G */
685+
INTEL_GPP(2, 127, 150, 224), /* GPP_H */
694686
};
695687

696688
static const struct intel_padgroup adls_community3_gpps[] = {
697-
ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
698-
ADL_GPP(1, 160, 175, 256), /* GPP_A */
699-
ADL_GPP(2, 176, 199, 288), /* GPP_C */
689+
INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
690+
INTEL_GPP(1, 160, 175, 256), /* GPP_A */
691+
INTEL_GPP(2, 176, 199, 288), /* GPP_C */
700692
};
701693

702694
static const struct intel_padgroup adls_community4_gpps[] = {
703-
ADL_GPP(0, 200, 207, 320), /* GPP_S */
704-
ADL_GPP(1, 208, 230, 352), /* GPP_E */
705-
ADL_GPP(2, 231, 245, 384), /* GPP_K */
706-
ADL_GPP(3, 246, 269, 416), /* GPP_F */
695+
INTEL_GPP(0, 200, 207, 320), /* GPP_S */
696+
INTEL_GPP(1, 208, 230, 352), /* GPP_E */
697+
INTEL_GPP(2, 231, 245, 384), /* GPP_K */
698+
INTEL_GPP(3, 246, 269, 416), /* GPP_F */
707699
};
708700

709701
static const struct intel_padgroup adls_community5_gpps[] = {
710-
ADL_GPP(0, 270, 294, 448), /* GPP_D */
711-
ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
702+
INTEL_GPP(0, 270, 294, 448), /* GPP_D */
703+
INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
712704
};
713705

714706
static const struct intel_community adls_communities[] = {

‎drivers/pinctrl/intel/pinctrl-baytrail.c‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1498,9 +1498,9 @@ static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
14981498

14991499
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
15001500
if (ret)
1501-
dev_err(dev, "failed to add GPIO pin range\n");
1501+
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
15021502

1503-
return ret;
1503+
return 0;
15041504
}
15051505

15061506
static int byt_gpio_probe(struct intel_pinctrl *vg)
@@ -1548,9 +1548,9 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
15481548

15491549
ret = devm_gpiochip_add_data(vg->dev, gc, vg);
15501550
if (ret)
1551-
dev_err(vg->dev, "failed adding byt-gpio chip\n");
1551+
return dev_err_probe(vg->dev, ret, "failed to register gpiochip\n");
15521552

1553-
return ret;
1553+
return 0;
15541554
}
15551555

15561556
static int byt_set_soc_data(struct intel_pinctrl *vg,
@@ -1601,21 +1601,17 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
16011601

16021602
vg->dev = dev;
16031603
ret = byt_set_soc_data(vg, soc_data);
1604-
if (ret) {
1605-
dev_err(dev, "failed to set soc data\n");
1606-
return ret;
1607-
}
1604+
if (ret)
1605+
return dev_err_probe(dev, ret, "failed to set soc data\n");
16081606

16091607
vg->pctldesc = byt_pinctrl_desc;
16101608
vg->pctldesc.name = dev_name(dev);
16111609
vg->pctldesc.pins = vg->soc->pins;
16121610
vg->pctldesc.npins = vg->soc->npins;
16131611

16141612
vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1615-
if (IS_ERR(vg->pctldev)) {
1616-
dev_err(dev, "failed to register pinctrl driver\n");
1617-
return PTR_ERR(vg->pctldev);
1618-
}
1613+
if (IS_ERR(vg->pctldev))
1614+
return dev_err_probe(dev, PTR_ERR(vg->pctldev), "failed to register pinctrl\n");
16191615

16201616
ret = byt_gpio_probe(vg);
16211617
if (ret)

‎drivers/pinctrl/intel/pinctrl-cannonlake.c‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,6 @@
2828
#define CNL_H_GPI_IS 0x100
2929
#define CNL_H_GPI_IE 0x120
3030

31-
#define CNL_GPP(r, s, e, g) \
32-
{ \
33-
.reg_num = (r), \
34-
.base = (s), \
35-
.size = ((e) - (s) + 1), \
36-
.gpio_base = (g), \
37-
}
38-
3931
#define CNL_LP_COMMUNITY(b, s, e, g) \
4032
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
4133

@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = {
362354
};
363355

364356
static const struct intel_padgroup cnlh_community0_gpps[] = {
365-
CNL_GPP(0, 0, 24, 0), /* GPP_A */
366-
CNL_GPP(1, 25, 50, 32), /* GPP_B */
357+
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
358+
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
367359
};
368360

369361
static const struct intel_padgroup cnlh_community1_gpps[] = {
370-
CNL_GPP(0, 51, 74, 64), /* GPP_C */
371-
CNL_GPP(1, 75, 98, 96), /* GPP_D */
372-
CNL_GPP(2, 99, 106, 128), /* GPP_G */
373-
CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
374-
CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
375-
CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
362+
INTEL_GPP(0, 51, 74, 64), /* GPP_C */
363+
INTEL_GPP(1, 75, 98, 96), /* GPP_D */
364+
INTEL_GPP(2, 99, 106, 128), /* GPP_G */
365+
INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
366+
INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */
367+
INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
376368
};
377369

378370
static const struct intel_padgroup cnlh_community3_gpps[] = {
379-
CNL_GPP(0, 155, 178, 192), /* GPP_K */
380-
CNL_GPP(1, 179, 202, 224), /* GPP_H */
381-
CNL_GPP(2, 203, 215, 256), /* GPP_E */
382-
CNL_GPP(3, 216, 239, 288), /* GPP_F */
383-
CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
371+
INTEL_GPP(0, 155, 178, 192), /* GPP_K */
372+
INTEL_GPP(1, 179, 202, 224), /* GPP_H */
373+
INTEL_GPP(2, 203, 215, 256), /* GPP_E */
374+
INTEL_GPP(3, 216, 239, 288), /* GPP_F */
375+
INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
384376
};
385377

386378
static const struct intel_padgroup cnlh_community4_gpps[] = {
387-
CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
388-
CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
389-
CNL_GPP(2, 269, 286, 320), /* GPP_I */
390-
CNL_GPP(3, 287, 298, 352), /* GPP_J */
379+
INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
380+
INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
381+
INTEL_GPP(2, 269, 286, 320), /* GPP_I */
382+
INTEL_GPP(3, 287, 298, 352), /* GPP_J */
391383
};
392384

393385
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = {
780772
};
781773

782774
static const struct intel_padgroup cnllp_community0_gpps[] = {
783-
CNL_GPP(0, 0, 24, 0), /* GPP_A */
784-
CNL_GPP(1, 25, 50, 32), /* GPP_B */
785-
CNL_GPP(2, 51, 58, 64), /* GPP_G */
786-
CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
775+
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
776+
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
777+
INTEL_GPP(2, 51, 58, 64), /* GPP_G */
778+
INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
787779
};
788780

789781
static const struct intel_padgroup cnllp_community1_gpps[] = {
790-
CNL_GPP(0, 68, 92, 96), /* GPP_D */
791-
CNL_GPP(1, 93, 116, 128), /* GPP_F */
792-
CNL_GPP(2, 117, 140, 160), /* GPP_H */
793-
CNL_GPP(3, 141, 172, 192), /* vGPIO */
794-
CNL_GPP(4, 173, 180, 224), /* vGPIO */
782+
INTEL_GPP(0, 68, 92, 96), /* GPP_D */
783+
INTEL_GPP(1, 93, 116, 128), /* GPP_F */
784+
INTEL_GPP(2, 117, 140, 160), /* GPP_H */
785+
INTEL_GPP(3, 141, 172, 192), /* vGPIO */
786+
INTEL_GPP(4, 173, 180, 224), /* vGPIO */
795787
};
796788

797789
static const struct intel_padgroup cnllp_community4_gpps[] = {
798-
CNL_GPP(0, 181, 204, 256), /* GPP_C */
799-
CNL_GPP(1, 205, 228, 288), /* GPP_E */
800-
CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
801-
CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
790+
INTEL_GPP(0, 181, 204, 256), /* GPP_C */
791+
INTEL_GPP(1, 205, 228, 288), /* GPP_E */
792+
INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
793+
INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
802794
};
803795

804796
static const struct intel_community cnllp_communities[] = {

‎drivers/pinctrl/intel/pinctrl-cedarfork.c‎

Lines changed: 15 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -21,13 +21,6 @@
2121
#define CDF_GPI_IS 0x200
2222
#define CDF_GPI_IE 0x230
2323

24-
#define CDF_GPP(r, s, e) \
25-
{ \
26-
.reg_num = (r), \
27-
.base = (s), \
28-
.size = ((e) - (s) + 1), \
29-
}
30-
3124
#define CDF_COMMUNITY(b, s, e, g) \
3225
INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
3326

@@ -288,24 +281,24 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
288281
};
289282

290283
static const struct intel_padgroup cdf_community0_gpps[] = {
291-
CDF_GPP(0, 0, 23), /* WEST2 */
292-
CDF_GPP(1, 24, 47), /* WEST3 */
293-
CDF_GPP(2, 48, 70), /* WEST01 */
294-
CDF_GPP(3, 71, 90), /* WEST5 */
295-
CDF_GPP(4, 91, 96), /* WESTC */
296-
CDF_GPP(5, 97, 101), /* WESTC_DFX */
297-
CDF_GPP(6, 102, 111), /* WESTA */
298-
CDF_GPP(7, 112, 123), /* WESTB */
299-
CDF_GPP(8, 124, 143), /* WESTD */
300-
CDF_GPP(9, 144, 144), /* WESTD_PECI */
301-
CDF_GPP(10, 145, 167), /* WESTF */
284+
INTEL_GPP(0, 0, 23, 0), /* WEST2 */
285+
INTEL_GPP(1, 24, 47, 24), /* WEST3 */
286+
INTEL_GPP(2, 48, 70, 48), /* WEST01 */
287+
INTEL_GPP(3, 71, 90, 71), /* WEST5 */
288+
INTEL_GPP(4, 91, 96, 91), /* WESTC */
289+
INTEL_GPP(5, 97, 101, 97), /* WESTC_DFX */
290+
INTEL_GPP(6, 102, 111, 102), /* WESTA */
291+
INTEL_GPP(7, 112, 123, 112), /* WESTB */
292+
INTEL_GPP(8, 124, 143, 124), /* WESTD */
293+
INTEL_GPP(9, 144, 144, 144), /* WESTD_PECI */
294+
INTEL_GPP(10, 145, 167, 145), /* WESTF */
302295
};
303296

304297
static const struct intel_padgroup cdf_community1_gpps[] = {
305-
CDF_GPP(0, 168, 191), /* EAST2 */
306-
CDF_GPP(1, 192, 202), /* EAST3 */
307-
CDF_GPP(2, 203, 225), /* EAST0 */
308-
CDF_GPP(3, 226, 236), /* EMMC */
298+
INTEL_GPP(0, 168, 191, 168), /* EAST2 */
299+
INTEL_GPP(1, 192, 202, 192), /* EAST3 */
300+
INTEL_GPP(2, 203, 225, 203), /* EAST0 */
301+
INTEL_GPP(3, 226, 236, 226), /* EMMC */
309302
};
310303

311304
static const struct intel_community cdf_communities[] = {

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