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Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "Algorithms: - Fix rmmod crash with x86/curve25519 - Add ECDH NIST P384 - Generate assembly files at build-time with perl scripts on arm - Switch to HMAC SHA512 DRBG as default DRBG Drivers: - Add sl3516 crypto engine - Add ECDH NIST P384 support in hisilicon/hpre - Add {ofb,cfb,ctr} over {aes,sm4} in hisilicon/sec - Add {ccm,gcm} over {aes,sm4} in hisilicon/sec - Enable omap hwrng driver for TI K3 family - Add support for AEAD algorithms in qce" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (142 commits) crypto: sl3516 - depends on HAS_IOMEM crypto: hisilicon/qm - implement for querying hardware tasks status. crypto: sl3516 - Fix build warning without CONFIG_PM MAINTAINERS: update caam crypto driver maintainers list crypto: nx - Fix numerous sparse byte-order warnings crypto: nx - Fix RCU warning in nx842_OF_upd_status crypto: api - Move crypto attr definitions out of crypto.h crypto: nx - Fix memcpy() over-reading in nonce crypto: hisilicon/sec - Fix spelling mistake "fallbcak" -> "fallback" crypto: sa2ul - Remove unused auth_len variable crypto: sl3516 - fix duplicated inclusion crypto: hisilicon/zip - adds the max shaper type rate crypto: hisilicon/hpre - adds the max shaper type rate crypto: hisilicon/sec - adds the max shaper type rate crypto: hisilicon/qm - supports to inquiry each function's QoS crypto: hisilicon/qm - add pf ping single vf function crypto: hisilicon/qm - merges the work initialization process into a single function crypto: hisilicon/qm - add the "alg_qos" file node crypto: hisilicon/qm - supports writing QoS int the host crypto: api - remove CRYPTOA_U32 and related functions ...
2 parents 31e798f + 9f38b67 commit 6159c49

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Lines changed: 7084 additions & 11175 deletions

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‎Documentation/devicetree/bindings/crypto/cortina,sl3516-crypto.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/cortina,sl3516-crypto.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SL3516 cryptographic offloader driver
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maintainers:
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- Corentin Labbe <clabbe@baylibre.com>
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properties:
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compatible:
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enum:
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- cortina,sl3516-crypto
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/cortina,gemini-clock.h>
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#include <dt-bindings/reset/cortina,gemini-reset.h>
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crypto@62000000 {
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compatible = "cortina,sl3516-crypto";
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reg = <0x62000000 0x10000>;
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interrupts = <7 IRQ_TYPE_EDGE_RISING>;
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resets = <&syscon GEMINI_RESET_SECURITY>;
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clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
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};

‎Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2018 Linaro Ltd.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel IXP4xx cryptographic engine
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |
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The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
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(Network Processing Engine). Since it is not a device on its own
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it is defined as a subnode of the NPE, if crypto support is
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available on the platform.
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properties:
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compatible:
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const: intel,ixp4xx-crypto
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intel,npe-handle:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: phandle to the NPE this crypto engine is using, the cell
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describing the NPE instance to be used.
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queue-rx:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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description: phandle to the RX queue on the NPE, the cell describing
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the queue instance to be used.
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queue-txready:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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description: phandle to the TX READY queue on the NPE, the cell describing
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the queue instance to be used.
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required:
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- compatible
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- intel,npe-handle
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- queue-rx
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- queue-txready
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additionalProperties: false

‎Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml‎

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reg:
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items:
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- description: NPE0 register range
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- description: NPE1 register range
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- description: NPE2 register range
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- description: NPE0 (NPE-A) register range
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- description: NPE1 (NPE-B) register range
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- description: NPE2 (NPE-C) register range
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crypto:
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$ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#
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type: object
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description: Optional node for the embedded crypto engine, the node
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should be named with the instance number of the NPE engine used for
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the crypto engine.
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required:
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- compatible
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examples:
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- |
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npe@c8006000 {
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npe: npe@c8006000 {
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compatible = "intel,ixp4xx-network-processing-engine";
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reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
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crypto {
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compatible = "intel,ixp4xx-crypto";
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intel,npe-handle = <&npe 2>;
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queue-rx = <&qmgr 30>;
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queue-txready = <&qmgr 29>;
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};
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};
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...

‎MAINTAINERS‎

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@@ -1811,6 +1811,7 @@ F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
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F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
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F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
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F: arch/arm/mach-gemini/
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F: drivers/crypto/gemini/
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F: drivers/net/ethernet/cortina/
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F: drivers/pinctrl/pinctrl-gemini.c
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F: drivers/rtc/rtc-ftrtc010.c
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F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
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F: arch/arm/mach-ixp4xx/
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F: drivers/clocksource/timer-ixp4xx.c
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F: drivers/crypto/ixp4xx_crypto.c
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F: drivers/gpio/gpio-ixp4xx.c
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F: drivers/irqchip/irq-ixp4xx.c
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F: include/linux/irqchip/irq-ixp4xx.h
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FREESCALE CAAM (Cryptographic Acceleration and Assurance Module) DRIVER
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M: Horia Geantă <horia.geanta@nxp.com>
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M: Aymen Sghaier <aymen.sghaier@nxp.com>
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M: Pankaj Gupta <pankaj.gupta@nxp.com>
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L: linux-crypto@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/crypto/fsl-sec4.txt
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S: Supported
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F: scripts/gdb/
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GEMINI CRYPTO DRIVER
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M: Corentin Labbe <clabbe@baylibre.com>
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L: linux-crypto@vger.kernel.org
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S: Maintained
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F: drivers/crypto/gemini/
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GEMTEK FM RADIO RECEIVER DRIVER
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M: Hans Verkuil <hverkuil@xs4all.nl>
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L: linux-media@vger.kernel.org
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F: Documentation/userspace-api/media/v4l/pixfmt-meta-intel-ipu3.rst
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F: drivers/staging/media/ipu3/
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INTEL IXP4XX CRYPTO SUPPORT
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M: Corentin Labbe <clabbe@baylibre.com>
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L: linux-crypto@vger.kernel.org
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S: Maintained
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F: drivers/crypto/ixp4xx_crypto.c
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INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
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M: Krzysztof Halasa <khalasa@piap.pl>
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S: Maintained
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F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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F: drivers/cpufreq/qcom-cpufreq-nvmem.c
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QUALCOMM CRYPTO DRIVERS
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M: Thara Gopinath <thara.gopinath@linaro.org>
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L: linux-crypto@vger.kernel.org
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: drivers/crypto/qce/
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QUALCOMM EMAC GIGABIT ETHERNET DRIVER
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M: Timur Tabi <timur@kernel.org>
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L: netdev@vger.kernel.org

‎arch/arm/crypto/Makefile‎

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@@ -45,20 +45,12 @@ poly1305-arm-y := poly1305-core.o poly1305-glue.o
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nhpoly1305-neon-y := nh-neon-core.o nhpoly1305-neon-glue.o
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curve25519-neon-y := curve25519-core.o curve25519-glue.o
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ifdef REGENERATE_ARM_CRYPTO
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quiet_cmd_perl = PERL $@
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cmd_perl = $(PERL) $(<) > $(@)
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$(src)/poly1305-core.S_shipped: $(src)/poly1305-armv4.pl
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$(obj)/%-core.S: $(src)/%-armv4.pl
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$(call cmd,perl)
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$(src)/sha256-core.S_shipped: $(src)/sha256-armv4.pl
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$(call cmd,perl)
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$(src)/sha512-core.S_shipped: $(src)/sha512-armv4.pl
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$(call cmd,perl)
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endif
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clean-files += poly1305-core.S sha256-core.S sha512-core.S
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# massage the perlasm code a bit so we only get the NEON routine if we need it

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