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jbrandebanguy11
jbrandeb
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anguy11
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i40e: field get conversion
Refactor the i40e driver to use FIELD_GET() for mask and shift reads, which reduces lines of code and adds clarity of intent. This code was generated by the following coccinelle/spatch script and then manually repaired. While making one of the conversions, an if() check was inverted to return early and avoid un-necessary indentation of the remainder of the function. In some other cases a stack variable was moved inside the block where it was used while doing cleanups/review. A couple places were changed to use le16_get_bits() instead of FIELD_GET with a le16_to_cpu combination. @get@ constant shift,mask; metavariable type T; expression a; @@ -(((T)(a) & mask) >> shift) +FIELD_GET(mask, a) and applied via: spatch --sp-file field_prep.cocci --in-place --dir \ drivers/net/ethernet/intel/ Cc: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Reviewed-by: Marcin Szycik <marcin.szycik@linux.intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
1 parent a8e0c7a commit 6258980

11 files changed

Lines changed: 145 additions & 226 deletions

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‎drivers/net/ethernet/intel/i40e/i40e_common.c‎

Lines changed: 21 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -664,11 +664,11 @@ int i40e_init_shared_code(struct i40e_hw *hw)
664664
hw->phy.get_link_info = true;
665665

666666
/* Determine port number and PF number*/
667-
port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
668-
>> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
667+
port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK,
668+
rd32(hw, I40E_PFGEN_PORTNUM));
669669
hw->port = (u8)port;
670-
ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
671-
I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
670+
ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK,
671+
rd32(hw, I40E_GLPCI_CAPSUP));
672672
func_rid = rd32(hw, I40E_PF_FUNC_RID);
673673
if (ari)
674674
hw->pf_id = (u8)(func_rid & 0xff);
@@ -986,9 +986,8 @@ int i40e_pf_reset(struct i40e_hw *hw)
986986
* The grst delay value is in 100ms units, and we'll wait a
987987
* couple counts longer to be sure we don't just miss the end.
988988
*/
989-
grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
990-
I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
991-
I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
989+
grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK,
990+
rd32(hw, I40E_GLGEN_RSTCTL));
992991

993992
/* It can take upto 15 secs for GRST steady state.
994993
* Bump it to 16 secs max to be safe.
@@ -1080,26 +1079,20 @@ void i40e_clear_hw(struct i40e_hw *hw)
10801079

10811080
/* get number of interrupts, queues, and VFs */
10821081
val = rd32(hw, I40E_GLPCI_CNF2);
1083-
num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1084-
I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1085-
num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1086-
I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1082+
num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val);
1083+
num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val);
10871084

10881085
val = rd32(hw, I40E_PFLAN_QALLOC);
1089-
base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1090-
I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1091-
j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1092-
I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1086+
base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val);
1087+
j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val);
10931088
if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
10941089
num_queues = (j - base_queue) + 1;
10951090
else
10961091
num_queues = 0;
10971092

10981093
val = rd32(hw, I40E_PF_VT_PFALLOC);
1099-
i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1100-
I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1101-
j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1102-
I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1094+
i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val);
1095+
j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val);
11031096
if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
11041097
num_vfs = (j - i) + 1;
11051098
else
@@ -1194,8 +1187,7 @@ static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
11941187
!hw->func_caps.led[idx])
11951188
return 0;
11961189
gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1197-
port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1198-
I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1190+
port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val);
11991191

12001192
/* if PRT_NUM_NA is 1 then this LED is not port specific, OR
12011193
* if it is not our port then ignore
@@ -1239,8 +1231,7 @@ u32 i40e_led_get(struct i40e_hw *hw)
12391231
if (!gpio_val)
12401232
continue;
12411233

1242-
mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1243-
I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1234+
mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val);
12441235
break;
12451236
}
12461237

@@ -4190,8 +4181,7 @@ i40e_validate_filter_settings(struct i40e_hw *hw,
41904181

41914182
/* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
41924183
val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4193-
fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4194-
>> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4184+
fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val);
41954185
if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
41964186
return -EINVAL;
41974187

@@ -4646,8 +4636,7 @@ int i40e_read_phy_register_clause22(struct i40e_hw *hw,
46464636
"PHY: Can't write command to external PHY.\n");
46474637
} else {
46484638
command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4649-
*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4650-
I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4639+
*value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
46514640
}
46524641

46534642
return status;
@@ -4756,8 +4745,7 @@ int i40e_read_phy_register_clause45(struct i40e_hw *hw,
47564745

47574746
if (!status) {
47584747
command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4759-
*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4760-
I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4748+
*value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
47614749
} else {
47624750
i40e_debug(hw, I40E_DEBUG_PHY,
47634751
"PHY: Can't read register value from external PHY.\n");
@@ -5902,9 +5890,8 @@ i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
59025890
u16 tnl_type;
59035891
u32 ti;
59045892

5905-
tnl_type = (le16_to_cpu(filters[i].element.flags) &
5906-
I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5907-
I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5893+
tnl_type = le16_get_bits(filters[i].element.flags,
5894+
I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
59085895

59095896
/* Due to hardware eccentricities, the VNI for Geneve is shifted
59105897
* one more byte further than normally used for Tenant ID in
@@ -5996,9 +5983,8 @@ i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
59965983
u16 tnl_type;
59975984
u32 ti;
59985985

5999-
tnl_type = (le16_to_cpu(filters[i].element.flags) &
6000-
I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6001-
I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5986+
tnl_type = le16_get_bits(filters[i].element.flags,
5987+
I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
60025988

60035989
/* Due to hardware eccentricities, the VNI for Geneve is shifted
60045990
* one more byte further than normally used for Tenant ID in

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