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Sam ProtsenkoSylwester Nawrocki
Sam Protsenko
authored and
Sylwester Nawrocki
committed
clk: samsung: exynos850: Implement CMU_CMGP domain
CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO). CMGP module encapsulates next blocks: - 8 GPIO lines - 1 GPADC - 2 USI blocks, each can be configured to provide one of UART/SPI/HSI2C serial interfaces Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211121232741.6967-5-semen.protsenko@linaro.org
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‎drivers/clk/samsung/clk-exynos850.c‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -492,6 +492,103 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
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.clk_name = "dout_clkcmu_apm_bus",
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};
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/* ---- CMU_CMGP ------------------------------------------------------------ */
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/* Register Offset definitions for CMU_CMGP (0x11c00000) */
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#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
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#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
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#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
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#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
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#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
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#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
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#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
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#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
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#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
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#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
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#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
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#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
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#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
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static const unsigned long cmgp_clk_regs[] __initconst = {
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CLK_CON_MUX_CLK_CMGP_ADC,
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CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
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CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
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CLK_CON_DIV_DIV_CLK_CMGP_ADC,
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CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
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CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
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CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
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CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
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CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
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};
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/* List of parent clocks for Muxes in CMU_CMGP */
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PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
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PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
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PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
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static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
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FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
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};
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static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
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MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
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CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
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MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
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CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
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MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
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CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
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};
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static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
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DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
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CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
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DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
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CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
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DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
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CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
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};
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static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
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GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
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"gout_clkcmu_cmgp_bus",
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CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
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GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
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"gout_clkcmu_cmgp_bus",
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CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
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GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
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"gout_clkcmu_cmgp_bus",
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CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, 0, 0),
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GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
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GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
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"gout_clkcmu_cmgp_bus",
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
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GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
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GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
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"gout_clkcmu_cmgp_bus",
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CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
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};
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static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
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.mux_clks = cmgp_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
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.div_clks = cmgp_div_clks,
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.nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
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.gate_clks = cmgp_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
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.fixed_clks = cmgp_fixed_clks,
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.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
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.nr_clk_ids = CMGP_NR_CLK,
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.clk_regs = cmgp_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
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.clk_name = "gout_clkcmu_cmgp_bus",
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};
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/* ---- CMU_HSI ------------------------------------------------------------- */
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/* Register Offset definitions for CMU_HSI (0x13400000) */
@@ -943,6 +1040,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
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{
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.compatible = "samsung,exynos850-cmu-apm",
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.data = &apm_cmu_info,
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}, {
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.compatible = "samsung,exynos850-cmu-cmgp",
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.data = &cmgp_cmu_info,
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}, {
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.compatible = "samsung,exynos850-cmu-hsi",
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.data = &hsi_cmu_info,

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