Skip to content

Commit 63a66eb

Browse files
geertugeertu
committed
pinctrl: renesas: r8a7779: Add bias pinconf support
Implement support for pull-up handling for the R-Car H1 SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dd966cfc916ef881051ec53bc3393dce7eea8e03.1679328215.git.geert+renesas@glider.be
1 parent 0256b6a commit 63a66eb

1 file changed

Lines changed: 328 additions & 7 deletions

File tree

‎drivers/pinctrl/renesas/pfc-r8a7779.c‎

Lines changed: 328 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,76 @@
1212
#include "sh_pfc.h"
1313

1414
#define CPU_ALL_GP(fn, sfx) \
15-
PORT_GP_32(0, fn, sfx), \
16-
PORT_GP_32(1, fn, sfx), \
17-
PORT_GP_32(2, fn, sfx), \
18-
PORT_GP_32(3, fn, sfx), \
19-
PORT_GP_32(4, fn, sfx), \
20-
PORT_GP_32(5, fn, sfx), \
21-
PORT_GP_9(6, fn, sfx)
15+
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16+
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
17+
PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18+
PORT_GP_1(2, 1, fn, sfx), \
19+
PORT_GP_1(2, 2, fn, sfx), \
20+
PORT_GP_1(2, 3, fn, sfx), \
21+
PORT_GP_1(2, 4, fn, sfx), \
22+
PORT_GP_1(2, 5, fn, sfx), \
23+
PORT_GP_1(2, 6, fn, sfx), \
24+
PORT_GP_1(2, 7, fn, sfx), \
25+
PORT_GP_1(2, 8, fn, sfx), \
26+
PORT_GP_1(2, 9, fn, sfx), \
27+
PORT_GP_1(2, 10, fn, sfx), \
28+
PORT_GP_1(2, 11, fn, sfx), \
29+
PORT_GP_1(2, 12, fn, sfx), \
30+
PORT_GP_1(2, 13, fn, sfx), \
31+
PORT_GP_1(2, 14, fn, sfx), \
32+
PORT_GP_1(2, 15, fn, sfx), \
33+
PORT_GP_1(2, 16, fn, sfx), \
34+
PORT_GP_1(2, 17, fn, sfx), \
35+
PORT_GP_1(2, 18, fn, sfx), \
36+
PORT_GP_1(2, 19, fn, sfx), \
37+
PORT_GP_1(2, 20, fn, sfx), \
38+
PORT_GP_1(2, 21, fn, sfx), \
39+
PORT_GP_1(2, 22, fn, sfx), \
40+
PORT_GP_1(2, 23, fn, sfx), \
41+
PORT_GP_1(2, 24, fn, sfx), \
42+
PORT_GP_1(2, 25, fn, sfx), \
43+
PORT_GP_1(2, 26, fn, sfx), \
44+
PORT_GP_1(2, 27, fn, sfx), \
45+
PORT_GP_1(2, 28, fn, sfx), \
46+
PORT_GP_1(2, 29, fn, sfx), \
47+
PORT_GP_CFG_1(2, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
48+
PORT_GP_CFG_1(2, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
49+
PORT_GP_CFG_25(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
50+
PORT_GP_1(3, 25, fn, sfx), \
51+
PORT_GP_1(3, 26, fn, sfx), \
52+
PORT_GP_1(3, 27, fn, sfx), \
53+
PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
54+
PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
55+
PORT_GP_CFG_1(3, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
56+
PORT_GP_CFG_1(3, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
57+
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
58+
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
59+
PORT_GP_CFG_9(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
60+
61+
#define CPU_ALL_NOGP(fn) \
62+
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_UP), \
63+
PIN_NOGP_CFG(D0, "D0", fn, SH_PFC_PIN_CFG_PULL_UP), \
64+
PIN_NOGP_CFG(D1, "D1", fn, SH_PFC_PIN_CFG_PULL_UP), \
65+
PIN_NOGP_CFG(D2, "D2", fn, SH_PFC_PIN_CFG_PULL_UP), \
66+
PIN_NOGP_CFG(D3, "D3", fn, SH_PFC_PIN_CFG_PULL_UP), \
67+
PIN_NOGP_CFG(D4, "D4", fn, SH_PFC_PIN_CFG_PULL_UP), \
68+
PIN_NOGP_CFG(D5, "D5", fn, SH_PFC_PIN_CFG_PULL_UP), \
69+
PIN_NOGP_CFG(D6, "D6", fn, SH_PFC_PIN_CFG_PULL_UP), \
70+
PIN_NOGP_CFG(D7, "D7", fn, SH_PFC_PIN_CFG_PULL_UP), \
71+
PIN_NOGP_CFG(D8, "D8", fn, SH_PFC_PIN_CFG_PULL_UP), \
72+
PIN_NOGP_CFG(D9, "D9", fn, SH_PFC_PIN_CFG_PULL_UP), \
73+
PIN_NOGP_CFG(D10, "D10", fn, SH_PFC_PIN_CFG_PULL_UP), \
74+
PIN_NOGP_CFG(D11, "D11", fn, SH_PFC_PIN_CFG_PULL_UP), \
75+
PIN_NOGP_CFG(D12, "D12", fn, SH_PFC_PIN_CFG_PULL_UP), \
76+
PIN_NOGP_CFG(D13, "D13", fn, SH_PFC_PIN_CFG_PULL_UP), \
77+
PIN_NOGP_CFG(D14, "D14", fn, SH_PFC_PIN_CFG_PULL_UP), \
78+
PIN_NOGP_CFG(D15, "D15", fn, SH_PFC_PIN_CFG_PULL_UP), \
79+
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \
80+
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
81+
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
82+
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \
83+
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
84+
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
2285

2386
enum {
2487
PINMUX_RESERVED = 0,
@@ -1390,8 +1453,17 @@ static const u16 pinmux_data[] = {
13901453
PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
13911454
};
13921455

1456+
/*
1457+
* Pins not associated with a GPIO port.
1458+
*/
1459+
enum {
1460+
GP_ASSIGN_LAST(),
1461+
NOGP_ALL(),
1462+
};
1463+
13931464
static const struct sh_pfc_pin pinmux_pins[] = {
13941465
PINMUX_GPIO_GP_ALL(),
1466+
PINMUX_NOGP_ALL(),
13951467
};
13961468

13971469
/* - DU0 -------------------------------------------------------------------- */
@@ -3922,8 +3994,256 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
39223994
{ /* sentinel */ }
39233995
};
39243996

3997+
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3998+
{ PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) {
3999+
[ 0] = RCAR_GP_PIN(0, 2), /* A0 */
4000+
[ 1] = RCAR_GP_PIN(5, 0), /* A1 */
4001+
[ 2] = RCAR_GP_PIN(5, 1), /* A2 */
4002+
[ 3] = RCAR_GP_PIN(5, 2), /* A3 */
4003+
[ 4] = RCAR_GP_PIN(5, 3), /* A4 */
4004+
[ 5] = RCAR_GP_PIN(5, 4), /* A5 */
4005+
[ 6] = RCAR_GP_PIN(5, 5), /* A6 */
4006+
[ 7] = RCAR_GP_PIN(5, 6), /* A7 */
4007+
[ 8] = RCAR_GP_PIN(5, 7), /* A8 */
4008+
[ 9] = RCAR_GP_PIN(5, 8), /* A9 */
4009+
[10] = RCAR_GP_PIN(5, 9), /* A10 */
4010+
[11] = RCAR_GP_PIN(5, 10), /* A11 */
4011+
[12] = RCAR_GP_PIN(5, 11), /* A12 */
4012+
[13] = RCAR_GP_PIN(5, 12), /* A13 */
4013+
[14] = RCAR_GP_PIN(5, 13), /* A14 */
4014+
[15] = RCAR_GP_PIN(5, 14), /* A15 */
4015+
[16] = RCAR_GP_PIN(5, 15), /* A16 */
4016+
[17] = RCAR_GP_PIN(0, 3), /* A17 */
4017+
[18] = RCAR_GP_PIN(0, 4), /* A18 */
4018+
[19] = RCAR_GP_PIN(0, 5), /* A19 */
4019+
[20] = RCAR_GP_PIN(0, 6), /* A20 */
4020+
[21] = RCAR_GP_PIN(0, 7), /* A21 */
4021+
[22] = RCAR_GP_PIN(0, 8), /* A22 */
4022+
[23] = RCAR_GP_PIN(0, 9), /* A23 */
4023+
[24] = RCAR_GP_PIN(0, 10), /* A24 */
4024+
[25] = RCAR_GP_PIN(0, 11), /* A25 */
4025+
[26] = RCAR_GP_PIN(0, 15), /* EX_CS0# */
4026+
[27] = RCAR_GP_PIN(0, 16), /* EX_CS1# */
4027+
[28] = RCAR_GP_PIN(0, 17), /* EX_CS2# */
4028+
[29] = RCAR_GP_PIN(0, 18), /* EX_CS3# */
4029+
[30] = RCAR_GP_PIN(0, 19), /* EX_CS4# */
4030+
[31] = RCAR_GP_PIN(0, 20), /* EX_CS5# */
4031+
} },
4032+
{ PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) {
4033+
[ 0] = PIN_PRESETOUT_N, /* PRESETOUT# */
4034+
[ 1] = RCAR_GP_PIN(0, 21), /* BS# */
4035+
[ 2] = RCAR_GP_PIN(0, 22), /* RD/WR# */
4036+
[ 3] = RCAR_GP_PIN(5, 17), /* WE0# */
4037+
[ 4] = RCAR_GP_PIN(5, 18), /* WE1# */
4038+
[ 5] = RCAR_GP_PIN(5, 19), /* EX_WAIT0 */
4039+
[ 6] = RCAR_GP_PIN(0, 0), /* AVS1 */
4040+
[ 7] = RCAR_GP_PIN(0, 1), /* AVS2 */
4041+
[ 8] = SH_PFC_PIN_NONE,
4042+
[ 9] = SH_PFC_PIN_NONE,
4043+
[10] = PIN_TRST_N, /* TRST# */
4044+
[11] = PIN_TCK, /* TCK */
4045+
[12] = PIN_TMS, /* TMS */
4046+
[13] = PIN_TDI, /* TDI */
4047+
[14] = PIN_TDO, /* TDO */
4048+
[15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
4049+
[16] = PIN_D0, /* D0 */
4050+
[17] = PIN_D1, /* D1 */
4051+
[18] = PIN_D2, /* D2 */
4052+
[19] = PIN_D3, /* D3 */
4053+
[20] = PIN_D4, /* D4 */
4054+
[21] = PIN_D5, /* D5 */
4055+
[22] = PIN_D6, /* D6 */
4056+
[23] = PIN_D7, /* D7 */
4057+
[24] = PIN_D8, /* D8 */
4058+
[25] = PIN_D9, /* D9 */
4059+
[26] = PIN_D10, /* D10 */
4060+
[27] = PIN_D11, /* D11 */
4061+
[28] = PIN_D12, /* D12 */
4062+
[29] = PIN_D13, /* D13 */
4063+
[30] = PIN_D14, /* D14 */
4064+
[31] = PIN_D15, /* D15 */
4065+
} },
4066+
{ PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) {
4067+
[ 0] = RCAR_GP_PIN(0, 23), /* DU0_DR0 */
4068+
[ 1] = RCAR_GP_PIN(0, 24), /* DU0_DR1 */
4069+
[ 2] = RCAR_GP_PIN(5, 23), /* DU0_DR2 */
4070+
[ 3] = RCAR_GP_PIN(5, 24), /* DU0_DR3 */
4071+
[ 4] = RCAR_GP_PIN(5, 25), /* DU0_DR4 */
4072+
[ 5] = RCAR_GP_PIN(5, 26), /* DU0_DR5 */
4073+
[ 6] = RCAR_GP_PIN(5, 27), /* DU0_DR6 */
4074+
[ 7] = RCAR_GP_PIN(5, 28), /* DU0_DR7 */
4075+
[ 8] = RCAR_GP_PIN(0, 25), /* DU0_DG0 */
4076+
[ 9] = RCAR_GP_PIN(0, 26), /* DU0_DG1 */
4077+
[10] = RCAR_GP_PIN(5, 29), /* DU0_DG2 */
4078+
[11] = RCAR_GP_PIN(5, 30), /* DU0_DG3 */
4079+
[12] = RCAR_GP_PIN(5, 31), /* DU0_DG4 */
4080+
[13] = RCAR_GP_PIN(6, 0), /* DU0_DG5 */
4081+
[14] = RCAR_GP_PIN(6, 1), /* DU0_DG6 */
4082+
[15] = RCAR_GP_PIN(6, 2), /* DU0_DG7 */
4083+
[16] = RCAR_GP_PIN(0, 27), /* DU0_DB0 */
4084+
[17] = RCAR_GP_PIN(0, 28), /* DU0_DB1 */
4085+
[18] = RCAR_GP_PIN(6, 3), /* DU0_DB2 */
4086+
[19] = RCAR_GP_PIN(6, 4), /* DU0_DB3 */
4087+
[20] = RCAR_GP_PIN(6, 5), /* DU0_DB4 */
4088+
[21] = RCAR_GP_PIN(6, 6), /* DU0_DB5 */
4089+
[22] = RCAR_GP_PIN(6, 7), /* DU0_DB6 */
4090+
[23] = RCAR_GP_PIN(6, 8), /* DU0_DB7 */
4091+
[24] = RCAR_GP_PIN(0, 29), /* DU0_DOTCLKIN */
4092+
[25] = RCAR_GP_PIN(5, 20), /* DU0_DOTCLKOUT0 */
4093+
[26] = RCAR_GP_PIN(5, 21), /* DU0_HSYNC */
4094+
[27] = RCAR_GP_PIN(5, 22), /* DU0_VSYNC */
4095+
[28] = RCAR_GP_PIN(0, 31), /* DU0_EXODDF */
4096+
[29] = RCAR_GP_PIN(1, 0), /* DU0_DISP */
4097+
[30] = RCAR_GP_PIN(1, 1), /* DU0_CDE */
4098+
[31] = RCAR_GP_PIN(0, 30), /* DU0_DOTCLKOUT1 */
4099+
} },
4100+
{ PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) {
4101+
[ 0] = RCAR_GP_PIN(1, 2), /* DU1_DR0 */
4102+
[ 1] = RCAR_GP_PIN(1, 3), /* DU1_DR1 */
4103+
[ 2] = RCAR_GP_PIN(1, 4), /* DU1_DR2 */
4104+
[ 3] = RCAR_GP_PIN(1, 5), /* DU1_DR3 */
4105+
[ 4] = RCAR_GP_PIN(1, 6), /* DU1_DR4 */
4106+
[ 5] = RCAR_GP_PIN(1, 7), /* DU1_DR5 */
4107+
[ 6] = RCAR_GP_PIN(1, 8), /* DU1_DR6 */
4108+
[ 7] = RCAR_GP_PIN(1, 9), /* DU1_DR7 */
4109+
[ 8] = RCAR_GP_PIN(1, 10), /* DU1_DG0 */
4110+
[ 9] = RCAR_GP_PIN(1, 11), /* DU1_DG1 */
4111+
[10] = RCAR_GP_PIN(1, 12), /* DU1_DG2 */
4112+
[11] = RCAR_GP_PIN(1, 13), /* DU1_DG3 */
4113+
[12] = RCAR_GP_PIN(1, 14), /* DU1_DG4 */
4114+
[13] = RCAR_GP_PIN(1, 15), /* DU1_DG5 */
4115+
[14] = RCAR_GP_PIN(1, 16), /* DU1_DG6 */
4116+
[15] = RCAR_GP_PIN(1, 17), /* DU1_DG7 */
4117+
[16] = RCAR_GP_PIN(1, 18), /* DU1_DB0 */
4118+
[17] = RCAR_GP_PIN(1, 19), /* DU1_DB1 */
4119+
[18] = RCAR_GP_PIN(1, 20), /* DU1_DB2 */
4120+
[19] = RCAR_GP_PIN(1, 21), /* DU1_DB3 */
4121+
[20] = RCAR_GP_PIN(1, 22), /* DU1_DB4 */
4122+
[21] = RCAR_GP_PIN(1, 23), /* DU1_DB5 */
4123+
[22] = RCAR_GP_PIN(1, 24), /* DU1_DB6 */
4124+
[23] = RCAR_GP_PIN(1, 25), /* DU1_DB7 */
4125+
[24] = RCAR_GP_PIN(1, 26), /* DU1_DOTCLKIN */
4126+
[25] = RCAR_GP_PIN(1, 27), /* DU1_DOTCLKOUT */
4127+
[26] = RCAR_GP_PIN(1, 28), /* DU1_HSYNC */
4128+
[27] = RCAR_GP_PIN(1, 29), /* DU1_VSYNC */
4129+
[28] = RCAR_GP_PIN(1, 30), /* DU1_EXODDF */
4130+
[29] = RCAR_GP_PIN(1, 31), /* DU1_DISP */
4131+
[30] = RCAR_GP_PIN(2, 0), /* DU1_CDE */
4132+
[31] = SH_PFC_PIN_NONE,
4133+
} },
4134+
{ PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) {
4135+
[ 0] = RCAR_GP_PIN(2, 30), /* VI1_CLK */
4136+
[ 1] = SH_PFC_PIN_NONE,
4137+
[ 2] = SH_PFC_PIN_NONE,
4138+
[ 3] = RCAR_GP_PIN(2, 31), /* VI1_HSYNC# */
4139+
[ 4] = RCAR_GP_PIN(3, 0), /* VI1_VSYNC# */
4140+
[ 5] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */
4141+
[ 6] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */
4142+
[ 7] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */
4143+
[ 8] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */
4144+
[ 9] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */
4145+
[10] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */
4146+
[11] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */
4147+
[12] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */
4148+
[13] = RCAR_GP_PIN(3, 9), /* VI1_G0 */
4149+
[14] = RCAR_GP_PIN(3, 10), /* VI1_G1 */
4150+
[15] = RCAR_GP_PIN(3, 11), /* VI1_G2 */
4151+
[16] = RCAR_GP_PIN(3, 12), /* VI1_G3 */
4152+
[17] = RCAR_GP_PIN(3, 13), /* VI1_G4 */
4153+
[18] = RCAR_GP_PIN(3, 14), /* VI1_G5 */
4154+
[19] = RCAR_GP_PIN(3, 15), /* VI1_G6 */
4155+
[20] = RCAR_GP_PIN(3, 16), /* VI1_G7 */
4156+
[21] = SH_PFC_PIN_NONE,
4157+
[22] = SH_PFC_PIN_NONE,
4158+
[23] = SH_PFC_PIN_NONE,
4159+
[24] = SH_PFC_PIN_NONE,
4160+
[25] = SH_PFC_PIN_NONE,
4161+
[26] = SH_PFC_PIN_NONE,
4162+
[27] = SH_PFC_PIN_NONE,
4163+
[28] = SH_PFC_PIN_NONE,
4164+
[29] = SH_PFC_PIN_NONE,
4165+
[30] = SH_PFC_PIN_NONE,
4166+
[31] = SH_PFC_PIN_NONE,
4167+
} },
4168+
{ PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) {
4169+
[ 0] = RCAR_GP_PIN(3, 30), /* SSI_SCK0129 */
4170+
[ 1] = RCAR_GP_PIN(3, 31), /* SSI_WS0129 */
4171+
[ 2] = RCAR_GP_PIN(4, 0), /* SSI_SDATA0 */
4172+
[ 3] = RCAR_GP_PIN(4, 1), /* SSI_SDATA1 */
4173+
[ 4] = RCAR_GP_PIN(4, 2), /* SSI_SDATA2 */
4174+
[ 5] = RCAR_GP_PIN(4, 3), /* SSI_SCK34 */
4175+
[ 6] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
4176+
[ 7] = RCAR_GP_PIN(4, 5), /* SSI_SDATA3 */
4177+
[ 8] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4 */
4178+
[ 9] = RCAR_GP_PIN(4, 7), /* SSI_SCK5 */
4179+
[10] = RCAR_GP_PIN(4, 8), /* SSI_WS5 */
4180+
[11] = RCAR_GP_PIN(4, 9), /* SSI_SDATA5 */
4181+
[12] = RCAR_GP_PIN(4, 10), /* SSI_SCK6 */
4182+
[13] = RCAR_GP_PIN(4, 11), /* SSI_WS6 */
4183+
[14] = RCAR_GP_PIN(4, 12), /* SSI_SDATA6 */
4184+
[15] = RCAR_GP_PIN(4, 13), /* SSI_SCK78 */
4185+
[16] = RCAR_GP_PIN(4, 14), /* SSI_WS78 */
4186+
[17] = RCAR_GP_PIN(4, 15), /* SSI_SDATA7 */
4187+
[18] = RCAR_GP_PIN(4, 16), /* SSI_SDATA8 */
4188+
[19] = SH_PFC_PIN_NONE,
4189+
[20] = RCAR_GP_PIN(3, 17), /* SD0_CLK */
4190+
[21] = RCAR_GP_PIN(3, 18), /* SD0_CMD */
4191+
[22] = RCAR_GP_PIN(3, 21), /* SD0_DAT0 */
4192+
[23] = RCAR_GP_PIN(3, 22), /* SD0_DAT1 */
4193+
[24] = RCAR_GP_PIN(3, 23), /* SD0_DAT2 */
4194+
[25] = RCAR_GP_PIN(3, 24), /* SD0_DAT3 */
4195+
[26] = RCAR_GP_PIN(3, 19), /* SD0_CD */
4196+
[27] = RCAR_GP_PIN(3, 20), /* SD0_WP */
4197+
[28] = RCAR_GP_PIN(3, 28), /* AUDIO_CLKA */
4198+
[29] = RCAR_GP_PIN(3, 29), /* AUDIO_CLKB */
4199+
[30] = SH_PFC_PIN_NONE,
4200+
[31] = SH_PFC_PIN_NONE,
4201+
} },
4202+
{ PINMUX_BIAS_REG("PUPR6", 0xfffc0118, "N/A", 0) {
4203+
[ 0] = RCAR_GP_PIN(4, 26), /* PENC0 */
4204+
[ 1] = RCAR_GP_PIN(4, 27), /* PENC1 */
4205+
[ 2] = RCAR_GP_PIN(4, 28), /* PENC2 */
4206+
[ 3] = SH_PFC_PIN_NONE,
4207+
[ 4] = SH_PFC_PIN_NONE,
4208+
[ 5] = RCAR_GP_PIN(4, 20), /* HTX0 */
4209+
[ 6] = RCAR_GP_PIN(4, 21), /* HRX0 */
4210+
[ 7] = RCAR_GP_PIN(4, 17), /* HSCK0 */
4211+
[ 8] = RCAR_GP_PIN(4, 18), /* HCTS0# */
4212+
[ 9] = RCAR_GP_PIN(4, 19), /* HRTS0# */
4213+
[10] = RCAR_GP_PIN(4, 22), /* HSPI_CLK0 */
4214+
[11] = RCAR_GP_PIN(4, 23), /* HSPI_CS0# */
4215+
[12] = RCAR_GP_PIN(4, 24), /* HSPI_TX0 */
4216+
[13] = RCAR_GP_PIN(4, 25), /* HSPI_RX0 */
4217+
[14] = RCAR_GP_PIN(4, 29), /* FMCLK */
4218+
[15] = RCAR_GP_PIN(4, 30), /* BPFCLK */
4219+
[16] = RCAR_GP_PIN(4, 31), /* FMIN */
4220+
[17] = RCAR_GP_PIN(0, 12), /* CLKOUT */
4221+
[18] = RCAR_GP_PIN(0, 13), /* CS0# */
4222+
[19] = RCAR_GP_PIN(0, 14), /* CS1#/A26 */
4223+
[20] = RCAR_GP_PIN(5, 16), /* RD# */
4224+
[21] = SH_PFC_PIN_NONE,
4225+
[22] = SH_PFC_PIN_NONE,
4226+
[23] = SH_PFC_PIN_NONE,
4227+
[24] = SH_PFC_PIN_NONE,
4228+
[25] = SH_PFC_PIN_NONE,
4229+
[26] = SH_PFC_PIN_NONE,
4230+
[27] = SH_PFC_PIN_NONE,
4231+
[28] = SH_PFC_PIN_NONE,
4232+
[29] = SH_PFC_PIN_NONE,
4233+
[30] = SH_PFC_PIN_NONE,
4234+
[31] = SH_PFC_PIN_NONE,
4235+
} },
4236+
{ /* sentinel */ }
4237+
};
4238+
4239+
static const struct sh_pfc_soc_operations r8a7779_pfc_ops = {
4240+
.get_bias = rcar_pinmux_get_bias,
4241+
.set_bias = rcar_pinmux_set_bias,
4242+
};
4243+
39254244
const struct sh_pfc_soc_info r8a7779_pinmux_info = {
39264245
.name = "r8a7779_pfc",
4246+
.ops = &r8a7779_pfc_ops,
39274247

39284248
.unlock_reg = 0xfffc0000, /* PMMR */
39294249

@@ -3937,6 +4257,7 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
39374257
.nr_functions = ARRAY_SIZE(pinmux_functions),
39384258

39394259
.cfg_regs = pinmux_config_regs,
4260+
.bias_regs = pinmux_bias_regs,
39404261

39414262
.pinmux_data = pinmux_data,
39424263
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

0 commit comments

Comments
 (0)