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Merge tag 'mmc-v5.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull mmc fixes from Ulf Hansson: "MMC core: - Fix initialization for eMMC's HS200/HS400 mode MMC host: - sdhci-msm: Reset GCC_SDCC_BCR register to prevent timeout issues - sunxi-mmc: Fix DMA descriptors allocated above 32 bits" * tag 'mmc-v5.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-msm: Reset GCC_SDCC_BCR register for SDHC mmc: sunxi-mmc: Fix DMA descriptors allocated above 32 bits mmc: core: Set HS clock speed before sending HS CMD13
2 parents 5fa576d + 3e5a8e8 commit 6426792

3 files changed

Lines changed: 64 additions & 6 deletions

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drivers/mmc/core/mmc.c

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1384,13 +1384,17 @@ static int mmc_select_hs400es(struct mmc_card *card)
13841384
goto out_err;
13851385
}
13861386

1387+
/*
1388+
* Bump to HS timing and frequency. Some cards don't handle
1389+
* SEND_STATUS reliably at the initial frequency.
1390+
*/
13871391
mmc_set_timing(host, MMC_TIMING_MMC_HS);
1392+
mmc_set_bus_speed(card);
1393+
13881394
err = mmc_switch_status(card, true);
13891395
if (err)
13901396
goto out_err;
13911397

1392-
mmc_set_clock(host, card->ext_csd.hs_max_dtr);
1393-
13941398
/* Switch card to DDR with strobe bit */
13951399
val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE;
13961400
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
@@ -1448,7 +1452,7 @@ static int mmc_select_hs400es(struct mmc_card *card)
14481452
static int mmc_select_hs200(struct mmc_card *card)
14491453
{
14501454
struct mmc_host *host = card->host;
1451-
unsigned int old_timing, old_signal_voltage;
1455+
unsigned int old_timing, old_signal_voltage, old_clock;
14521456
int err = -EINVAL;
14531457
u8 val;
14541458

@@ -1479,8 +1483,17 @@ static int mmc_select_hs200(struct mmc_card *card)
14791483
false, true, MMC_CMD_RETRIES);
14801484
if (err)
14811485
goto err;
1486+
1487+
/*
1488+
* Bump to HS timing and frequency. Some cards don't handle
1489+
* SEND_STATUS reliably at the initial frequency.
1490+
* NB: We can't move to full (HS200) speeds until after we've
1491+
* successfully switched over.
1492+
*/
14821493
old_timing = host->ios.timing;
1494+
old_clock = host->ios.clock;
14831495
mmc_set_timing(host, MMC_TIMING_MMC_HS200);
1496+
mmc_set_clock(card->host, card->ext_csd.hs_max_dtr);
14841497

14851498
/*
14861499
* For HS200, CRC errors are not a reliable way to know the
@@ -1493,8 +1506,10 @@ static int mmc_select_hs200(struct mmc_card *card)
14931506
* mmc_select_timing() assumes timing has not changed if
14941507
* it is a switch error.
14951508
*/
1496-
if (err == -EBADMSG)
1509+
if (err == -EBADMSG) {
1510+
mmc_set_clock(host, old_clock);
14971511
mmc_set_timing(host, old_timing);
1512+
}
14981513
}
14991514
err:
15001515
if (err) {

drivers/mmc/host/sdhci-msm.c

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include <linux/regulator/consumer.h>
1818
#include <linux/interconnect.h>
1919
#include <linux/pinctrl/consumer.h>
20+
#include <linux/reset.h>
2021

2122
#include "sdhci-pltfm.h"
2223
#include "cqhci.h"
@@ -2482,6 +2483,43 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
24822483
of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
24832484
}
24842485

2486+
static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
2487+
{
2488+
struct reset_control *reset;
2489+
int ret = 0;
2490+
2491+
reset = reset_control_get_optional_exclusive(dev, NULL);
2492+
if (IS_ERR(reset))
2493+
return dev_err_probe(dev, PTR_ERR(reset),
2494+
"unable to acquire core_reset\n");
2495+
2496+
if (!reset)
2497+
return ret;
2498+
2499+
ret = reset_control_assert(reset);
2500+
if (ret) {
2501+
reset_control_put(reset);
2502+
return dev_err_probe(dev, ret, "core_reset assert failed\n");
2503+
}
2504+
2505+
/*
2506+
* The hardware requirement for delay between assert/deassert
2507+
* is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
2508+
* ~125us (4/32768). To be on the safe side add 200us delay.
2509+
*/
2510+
usleep_range(200, 210);
2511+
2512+
ret = reset_control_deassert(reset);
2513+
if (ret) {
2514+
reset_control_put(reset);
2515+
return dev_err_probe(dev, ret, "core_reset deassert failed\n");
2516+
}
2517+
2518+
usleep_range(200, 210);
2519+
reset_control_put(reset);
2520+
2521+
return ret;
2522+
}
24852523

24862524
static int sdhci_msm_probe(struct platform_device *pdev)
24872525
{
@@ -2529,6 +2567,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
25292567

25302568
msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
25312569

2570+
ret = sdhci_msm_gcc_reset(&pdev->dev, host);
2571+
if (ret)
2572+
goto pltfm_free;
2573+
25322574
/* Setup SDCC bus voter clock. */
25332575
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
25342576
if (!IS_ERR(msm_host->bus_clk)) {

drivers/mmc/host/sunxi-mmc.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -377,8 +377,9 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
377377
pdes[i].buf_addr_ptr1 =
378378
cpu_to_le32(sg_dma_address(&data->sg[i]) >>
379379
host->cfg->idma_des_shift);
380-
pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
381-
host->cfg->idma_des_shift);
380+
pdes[i].buf_addr_ptr2 =
381+
cpu_to_le32(next_desc >>
382+
host->cfg->idma_des_shift);
382383
}
383384

384385
pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);

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