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Marc ZyngierKAGA-KOKO
authored andcommitted
irqchip/gic-v3: Drop support for custom PPI partitions
The only thing getting in the way of correctly handling PPIs the way they were intended is the GICv3 hack that deals with PPI partitions. Remove that code, allowing the common code to kick in. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Will Deacon <will@kernel.org> Link: https://patch.msgid.link/20251020122944.3074811-22-maz@kernel.org
1 parent 4cdf481 commit 64b9738

2 files changed

Lines changed: 8 additions & 126 deletions

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drivers/irqchip/Kconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ config GIC_NON_BANKED
3636
config ARM_GIC_V3
3737
bool
3838
select IRQ_DOMAIN_HIERARCHY
39-
select PARTITION_PERCPU
4039
select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
4140
select HAVE_ARM_SMCCC_DISCOVERY
4241
select IRQ_MSI_IOMMU

drivers/irqchip/irq-gic-v3.c

Lines changed: 8 additions & 125 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626
#include <linux/irqchip/arm-gic-common.h>
2727
#include <linux/irqchip/arm-gic-v3.h>
2828
#include <linux/irqchip/arm-gic-v3-prio.h>
29-
#include <linux/irqchip/irq-partition-percpu.h>
3029
#include <linux/bitfield.h>
3130
#include <linux/bits.h>
3231
#include <linux/arm-smccc.h>
@@ -46,8 +45,6 @@ static u8 dist_prio_nmi __ro_after_init = GICV3_PRIO_NMI;
4645
#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2)
4746
#define FLAGS_WORKAROUND_INSECURE (1ULL << 3)
4847

49-
#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
50-
5148
static struct cpumask broken_rdists __read_mostly __maybe_unused;
5249

5350
struct redist_region {
@@ -68,11 +65,15 @@ struct gic_chip_data {
6865
u64 flags;
6966
bool has_rss;
7067
unsigned int ppi_nr;
71-
struct partition_desc **ppi_descs;
7268
struct partition_affinity *parts;
7369
unsigned int nr_parts;
7470
};
7571

72+
struct partition_affinity {
73+
cpumask_t mask;
74+
struct fwnode_handle *partition_id;
75+
};
76+
7677
#define T241_CHIPS_MAX 4
7778
static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly;
7879
static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum);
@@ -593,18 +594,6 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
593594
writeb_relaxed(prio, base + offset + index);
594595
}
595596

596-
static u32 __gic_get_ppi_index(irq_hw_number_t hwirq)
597-
{
598-
switch (__get_intid_range(hwirq)) {
599-
case PPI_RANGE:
600-
return hwirq - 16;
601-
case EPPI_RANGE:
602-
return hwirq - EPPI_BASE_INTID + 16;
603-
default:
604-
unreachable();
605-
}
606-
}
607-
608597
static int gic_irq_nmi_setup(struct irq_data *d)
609598
{
610599
struct irq_desc *desc = irq_to_desc(d->irq);
@@ -1628,13 +1617,6 @@ static int gic_irq_domain_translate(struct irq_domain *d,
16281617
case GIC_IRQ_TYPE_LPI: /* LPI */
16291618
*hwirq = fwspec->param[1];
16301619
break;
1631-
case GIC_IRQ_TYPE_PARTITION:
1632-
*hwirq = fwspec->param[1];
1633-
if (fwspec->param[1] >= 16)
1634-
*hwirq += EPPI_BASE_INTID - 16;
1635-
else
1636-
*hwirq += 16;
1637-
break;
16381620
default:
16391621
return -EINVAL;
16401622
}
@@ -1643,10 +1625,8 @@ static int gic_irq_domain_translate(struct irq_domain *d,
16431625

16441626
/*
16451627
* Make it clear that broken DTs are... broken.
1646-
* Partitioned PPIs are an unfortunate exception.
16471628
*/
1648-
WARN_ON(*type == IRQ_TYPE_NONE &&
1649-
fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1629+
WARN_ON(*type == IRQ_TYPE_NONE);
16501630
return 0;
16511631
}
16521632

@@ -1703,33 +1683,12 @@ static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
17031683
}
17041684
}
17051685

1706-
static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec,
1707-
irq_hw_number_t hwirq)
1708-
{
1709-
enum gic_intid_range range;
1710-
1711-
if (!gic_data.ppi_descs)
1712-
return false;
1713-
1714-
if (!is_of_node(fwspec->fwnode))
1715-
return false;
1716-
1717-
if (fwspec->param_count < 4 || !fwspec->param[3])
1718-
return false;
1719-
1720-
range = __get_intid_range(hwirq);
1721-
if (range != PPI_RANGE && range != EPPI_RANGE)
1722-
return false;
1723-
1724-
return true;
1725-
}
1726-
17271686
static int gic_irq_domain_select(struct irq_domain *d,
17281687
struct irq_fwspec *fwspec,
17291688
enum irq_domain_bus_token bus_token)
17301689
{
1731-
unsigned int type, ppi_idx;
17321690
irq_hw_number_t hwirq;
1691+
unsigned int type;
17331692
int ret;
17341693

17351694
/* Not for us */
@@ -1748,15 +1707,7 @@ static int gic_irq_domain_select(struct irq_domain *d,
17481707
if (WARN_ON_ONCE(ret))
17491708
return 0;
17501709

1751-
if (!fwspec_is_partitioned_ppi(fwspec, hwirq))
1752-
return d == gic_data.domain;
1753-
1754-
/*
1755-
* If this is a PPI and we have a 4th (non-null) parameter,
1756-
* then we need to match the partition domain.
1757-
*/
1758-
ppi_idx = __gic_get_ppi_index(hwirq);
1759-
return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]);
1710+
return d == gic_data.domain;
17601711
}
17611712

17621713
static int gic_irq_get_fwspec_info(struct irq_fwspec *fwspec, struct irq_fwspec_info *info)
@@ -1813,45 +1764,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
18131764
.get_fwspec_info = gic_irq_get_fwspec_info,
18141765
};
18151766

1816-
static int partition_domain_translate(struct irq_domain *d,
1817-
struct irq_fwspec *fwspec,
1818-
unsigned long *hwirq,
1819-
unsigned int *type)
1820-
{
1821-
unsigned long ppi_intid;
1822-
struct device_node *np;
1823-
unsigned int ppi_idx;
1824-
int ret;
1825-
1826-
if (!gic_data.ppi_descs)
1827-
return -ENOMEM;
1828-
1829-
np = of_find_node_by_phandle(fwspec->param[3]);
1830-
if (WARN_ON(!np))
1831-
return -EINVAL;
1832-
1833-
ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type);
1834-
if (WARN_ON_ONCE(ret))
1835-
return 0;
1836-
1837-
ppi_idx = __gic_get_ppi_index(ppi_intid);
1838-
ret = partition_translate_id(gic_data.ppi_descs[ppi_idx],
1839-
of_fwnode_handle(np));
1840-
if (ret < 0)
1841-
return ret;
1842-
1843-
*hwirq = ret;
1844-
*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1845-
1846-
return 0;
1847-
}
1848-
1849-
static const struct irq_domain_ops partition_domain_ops = {
1850-
.translate = partition_domain_translate,
1851-
.select = gic_irq_domain_select,
1852-
.get_fwspec_info = gic_irq_get_fwspec_info,
1853-
};
1854-
18551767
static bool gic_enable_quirk_msm8996(void *data)
18561768
{
18571769
struct gic_chip_data *d = data;
@@ -2174,12 +2086,7 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
21742086
if (!parts_node)
21752087
return;
21762088

2177-
gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
2178-
if (!gic_data.ppi_descs)
2179-
goto out_put_node;
2180-
21812089
nr_parts = of_get_child_count(parts_node);
2182-
21832090
if (!nr_parts)
21842091
goto out_put_node;
21852092

@@ -2235,30 +2142,6 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
22352142
gic_data.parts = parts;
22362143
gic_data.nr_parts = nr_parts;
22372144

2238-
for (i = 0; i < gic_data.ppi_nr; i++) {
2239-
unsigned int irq;
2240-
struct partition_desc *desc;
2241-
struct irq_fwspec ppi_fwspec = {
2242-
.fwnode = gic_data.fwnode,
2243-
.param_count = 3,
2244-
.param = {
2245-
[0] = GIC_IRQ_TYPE_PARTITION,
2246-
[1] = i,
2247-
[2] = IRQ_TYPE_NONE,
2248-
},
2249-
};
2250-
2251-
irq = irq_create_fwspec_mapping(&ppi_fwspec);
2252-
if (WARN_ON(!irq))
2253-
continue;
2254-
desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
2255-
irq, &partition_domain_ops);
2256-
if (WARN_ON(!desc))
2257-
continue;
2258-
2259-
gic_data.ppi_descs[i] = desc;
2260-
}
2261-
22622145
out_put_node:
22632146
of_node_put(parts_node);
22642147
}

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