Skip to content

Commit 65522e7

Browse files
cometzerokrzk
cometzero
authored and
krzk
committed
clk: samsung: exynosautov9: add fsys1 clock support
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/d4aa967538fed9667e9550a256e545026fc2fa8d.1659054220.git.chanho61.park@samsung.com
1 parent 3477b3c commit 65522e7

1 file changed

Lines changed: 130 additions & 0 deletions

File tree

‎drivers/clk/samsung/clk-exynosautov9.c‎

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1307,6 +1307,133 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
13071307
.clk_name = "dout_clkcmu_fsys0_bus",
13081308
};
13091309

1310+
/* ---- CMU_FSYS1 ---------------------------------------------------------- */
1311+
1312+
/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
1313+
#define PLL_LOCKTIME_PLL_MMC 0x0000
1314+
#define PLL_CON0_PLL_MMC 0x0100
1315+
#define PLL_CON3_PLL_MMC 0x010c
1316+
#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
1317+
#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
1318+
#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
1319+
1320+
#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
1321+
#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
1322+
1323+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
1324+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
1325+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
1326+
1327+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
1328+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
1329+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
1330+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
1331+
1332+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
1333+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
1334+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
1335+
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
1336+
1337+
static const unsigned long fsys1_clk_regs[] __initconst = {
1338+
PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
1339+
};
1340+
1341+
static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
1342+
PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
1343+
PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
1344+
};
1345+
1346+
/* List of parent clocks for Muxes in CMU_FSYS1 */
1347+
PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
1348+
PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
1349+
PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
1350+
PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
1351+
PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user",
1352+
"mout_fsys1_mmc_pll" };
1353+
1354+
static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1355+
MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
1356+
mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
1357+
MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p,
1358+
PLL_CON0_PLL_MMC, 4, 1),
1359+
MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
1360+
mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
1361+
4, 1),
1362+
MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
1363+
mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
1364+
4, 1),
1365+
MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
1366+
mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
1367+
0, 1),
1368+
};
1369+
1370+
static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1371+
DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
1372+
"mout_fsys1_mmc_card",
1373+
CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
1374+
};
1375+
1376+
static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1377+
GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
1378+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
1379+
21, CLK_IGNORE_UNUSED, 0),
1380+
GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
1381+
"dout_fsys1_mmc_card",
1382+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
1383+
21, CLK_SET_RATE_PARENT, 0),
1384+
GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
1385+
"dout_fsys1_mmc_card",
1386+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
1387+
21, 0, 0),
1388+
GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
1389+
"mout_fsys1_usbdrd_user",
1390+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
1391+
21, 0, 0),
1392+
GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
1393+
"mout_fsys1_usbdrd_user",
1394+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
1395+
21, 0, 0),
1396+
GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
1397+
"mout_fsys1_usbdrd_user",
1398+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
1399+
21, 0, 0),
1400+
GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
1401+
"mout_fsys1_usbdrd_user",
1402+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
1403+
21, 0, 0),
1404+
GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
1405+
"mout_fsys1_usbdrd_user",
1406+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
1407+
21, 0, 0),
1408+
GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
1409+
"mout_fsys1_usbdrd_user",
1410+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
1411+
21, 0, 0),
1412+
GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
1413+
"mout_fsys1_usbdrd_user",
1414+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
1415+
21, 0, 0),
1416+
GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
1417+
"mout_fsys1_usbdrd_user",
1418+
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
1419+
21, 0, 0),
1420+
};
1421+
1422+
static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1423+
.pll_clks = fsys1_pll_clks,
1424+
.nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
1425+
.mux_clks = fsys1_mux_clks,
1426+
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
1427+
.div_clks = fsys1_div_clks,
1428+
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
1429+
.gate_clks = fsys1_gate_clks,
1430+
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
1431+
.nr_clk_ids = FSYS1_NR_CLK,
1432+
.clk_regs = fsys1_clk_regs,
1433+
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
1434+
.clk_name = "dout_clkcmu_fsys1_bus",
1435+
};
1436+
13101437
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
13111438

13121439
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
@@ -1952,6 +2079,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
19522079
}, {
19532080
.compatible = "samsung,exynosautov9-cmu-fsys0",
19542081
.data = &fsys0_cmu_info,
2082+
}, {
2083+
.compatible = "samsung,exynosautov9-cmu-fsys1",
2084+
.data = &fsys1_cmu_info,
19552085
}, {
19562086
.compatible = "samsung,exynosautov9-cmu-fsys2",
19572087
.data = &fsys2_cmu_info,

0 commit comments

Comments
 (0)