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Andre-ARMwens
Andre-ARM
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wens
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clk: sunxi-ng: a523: add video mod clocks
Add the clocks driving the various video subsystems of the SoC: the "DE" display engine, the "DI" deinterlacer, the "G2D" 2D graphics system, the Mali "GPU", the "VE" video engine, its associated IOMMU, as well as the clocks for the various video output drivers (HDMI, DP, LCDs). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-8-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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‎drivers/clk/sunxi-ng/ccu-sun55i-a523.c‎

Lines changed: 238 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -364,6 +364,208 @@ static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524,
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24, 3, /* mux */
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0);
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/**************************************************************************
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* mod clocks *
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**************************************************************************/
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static const struct clk_hw *de_parents[] = {
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&pll_periph0_300M_clk.hw,
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&pll_periph0_400M_clk.hw,
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&pll_video3_4x_clk.common.hw,
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&pll_video3_3x_clk.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static const struct clk_hw *di_parents[] = {
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&pll_periph0_300M_clk.hw,
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&pll_periph0_400M_clk.hw,
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&pll_video0_4x_clk.common.hw,
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&pll_video1_4x_clk.common.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0x620,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static const struct clk_hw *g2d_parents[] = {
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&pll_periph0_400M_clk.hw,
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&pll_periph0_300M_clk.hw,
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&pll_video0_4x_clk.common.hw,
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&pll_video1_4x_clk.common.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0x630,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static const struct clk_hw *gpu_parents[] = {
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&pll_gpu_clk.common.hw,
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&pll_periph0_800M_clk.common.hw,
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&pll_periph0_600M_clk.hw,
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&pll_periph0_400M_clk.hw,
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&pll_periph0_300M_clk.hw,
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&pll_periph0_200M_clk.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
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0, 4, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static const struct clk_hw *ve_parents[] = {
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&pll_ve_clk.common.hw,
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&pll_periph0_480M_clk.common.hw,
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&pll_periph0_400M_clk.hw,
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&pll_periph0_300M_clk.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static const struct clk_parent_data iommu_parents[] = {
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{ .hw = &pll_periph0_600M_clk.hw },
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{ .hw = &pll_ddr_clk.common.hw },
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{ .hw = &pll_periph0_480M_clk.common.hw },
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{ .hw = &pll_periph0_400M_clk.hw },
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{ .hw = &pll_periph0_150M_clk.hw },
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{ .fw_name = "hosc" },
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};
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
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0x7b0,
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0, 5, /* M */
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0, 0, /* no P */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT,
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CCU_FEATURE_UPDATE_BIT);
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static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0);
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static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
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pll_periph0_2x_hws,
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0xb10, BIT(30), 36621, 0);
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static const struct clk_parent_data hdmi_cec_parents[] = {
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{ .fw_name = "losc" },
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{ .hw = &hdmi_cec_32k_clk.common.hw },
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};
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static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents,
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0xb10,
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24, 1, /* mux */
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BIT(31), /* gate */
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0);
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static const struct clk_parent_data mipi_dsi_parents[] = {
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{ .fw_name = "hosc" },
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{ .hw = &pll_periph0_200M_clk.hw },
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{ .hw = &pll_periph0_150M_clk.hw },
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};
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi0_clk, "mipi-dsi0",
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mipi_dsi_parents, 0xb24,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi1_clk, "mipi-dsi1",
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mipi_dsi_parents, 0xb28,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static const struct clk_hw *tcon_parents[] = {
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&pll_video0_4x_clk.common.hw,
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&pll_video1_4x_clk.common.hw,
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&pll_video2_4x_clk.common.hw,
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&pll_video3_4x_clk.common.hw,
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&pll_periph0_2x_clk.common.hw,
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&pll_video0_3x_clk.hw,
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&pll_video1_3x_clk.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
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0xb60,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
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0xb64,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static const struct clk_hw *tcon_tv_parents[] = {
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&pll_video0_4x_clk.common.hw,
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&pll_video1_4x_clk.common.hw,
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&pll_video2_4x_clk.common.hw,
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&pll_video3_4x_clk.common.hw,
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&pll_periph0_2x_clk.common.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2",
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tcon_tv_parents, 0xb68,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi0_clk, "combophy-dsi0",
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tcon_parents, 0xb6c,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi1_clk, "combophy-dsi1",
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tcon_parents, 0xb70,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_tv_parents,
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0xb80,
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0, 4, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_tv_parents,
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0xb84,
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0, 4, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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static const struct clk_hw *edp_parents[] = {
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&pll_video0_4x_clk.common.hw,
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&pll_video1_4x_clk.common.hw,
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&pll_video2_4x_clk.common.hw,
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&pll_video3_4x_clk.common.hw,
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&pll_periph0_2x_clk.common.hw,
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};
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static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_clk, "edp", edp_parents, 0xbb0,
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0, 4, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
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367569
/*
368570
* Contains all clocks that are controlled by a hardware register. They
369571
* have a (sunxi) .common member, which needs to be initialised by the common
@@ -394,6 +596,23 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
394596
&ahb_clk.common,
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&apb0_clk.common,
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&apb1_clk.common,
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&de_clk.common,
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&di_clk.common,
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&g2d_clk.common,
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&gpu_clk.common,
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&ve_clk.common,
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&iommu_clk.common,
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&hdmi_24M_clk.common,
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&hdmi_cec_32k_clk.common,
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&hdmi_cec_clk.common,
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&mipi_dsi0_clk.common,
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&mipi_dsi1_clk.common,
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&tcon_lcd0_clk.common,
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&tcon_lcd1_clk.common,
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&tcon_lcd2_clk.common,
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&tcon_tv0_clk.common,
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&tcon_tv1_clk.common,
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&edp_clk.common,
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};
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399618
static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
@@ -420,6 +639,7 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
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[CLK_PLL_PERIPH1_200M] = &pll_periph1_200M_clk.hw,
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[CLK_PLL_PERIPH1_160M] = &pll_periph1_160M_clk.hw,
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[CLK_PLL_PERIPH1_150M] = &pll_periph1_150M_clk.hw,
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[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
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[CLK_PLL_VIDEO0_8X] = &pll_video0_8x_clk.common.hw,
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[CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
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[CLK_PLL_VIDEO0_3X] = &pll_video0_3x_clk.hw,
@@ -442,6 +662,24 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
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[CLK_AHB] = &ahb_clk.common.hw,
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[CLK_APB0] = &apb0_clk.common.hw,
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[CLK_APB1] = &apb1_clk.common.hw,
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[CLK_DE] = &de_clk.common.hw,
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[CLK_DI] = &di_clk.common.hw,
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[CLK_G2D] = &g2d_clk.common.hw,
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[CLK_GPU] = &gpu_clk.common.hw,
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[CLK_VE] = &ve_clk.common.hw,
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[CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
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[CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
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[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
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[CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
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[CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
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[CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
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[CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
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[CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw,
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[CLK_COMBOPHY_DSI0] = &combophy_dsi0_clk.common.hw,
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[CLK_COMBOPHY_DSI1] = &combophy_dsi1_clk.common.hw,
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[CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
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[CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
682+
[CLK_EDP] = &edp_clk.common.hw,
445683
},
446684
};
447685

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