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tools arch x86: Sync the msr-index.h copy with the kernel sources
To pick up the changes in: 991625f ("x86/ibt: Add IBT feature, MSR and #CP handling") Addressing these tools/perf build warnings: diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h' That makes the beautification scripts to pick some new entries: $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after $ diff -u before after --- before 2022-03-29 16:23:07.678740040 -0300 +++ after 2022-03-29 16:23:16.960978524 -0300 @@ -220,6 +220,13 @@ [0x00000669] = "MC6_DEMOTION_POLICY_CONFIG", [0x00000680] = "LBR_NHM_FROM", [0x00000690] = "CORE_PERF_LIMIT_REASONS", + [0x000006a0] = "IA32_U_CET", + [0x000006a2] = "IA32_S_CET", + [0x000006a4] = "IA32_PL0_SSP", + [0x000006a5] = "IA32_PL1_SSP", + [0x000006a6] = "IA32_PL2_SSP", + [0x000006a7] = "IA32_PL3_SSP", + [0x000006a8] = "IA32_INT_SSP_TAB", [0x000006B0] = "GFX_PERF_LIMIT_REASONS", [0x000006B1] = "RING_PERF_LIMIT_REASONS", [0x000006c0] = "LBR_NHM_TO", $ And this gets rebuilt: CC /tmp/build/perf/trace/beauty/tracepoints/x86_msr.o LD /tmp/build/perf/trace/beauty/tracepoints/perf-in.o LD /tmp/build/perf/trace/beauty/perf-in.o CC /tmp/build/perf/util/amd-sample-raw.o LD /tmp/build/perf/util/perf-in.o LD /tmp/build/perf/perf-in.o LINK /tmp/build/perf/perf Now one can trace systemwide asking to see backtraces to where those MSRs are being read/written with: # perf trace -e msr:*_msr/max-stack=32/ --filter="msr>=IA32_U_CET && msr<=IA32_INT_SSP_TAB" ^C# If we use -v (verbose mode) we can see what it does behind the scenes: # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr>=IA32_U_CET && msr<=IA32_INT_SSP_TAB" Using CPUID AuthenticAMD-25-21-0 0x6a0 0x6a8 New filter for msr:read_msr: (msr>=0x6a0 && msr<=0x6a8) && (common_pid != 597499 && common_pid != 3313) 0x6a0 0x6a8 New filter for msr:write_msr: (msr>=0x6a0 && msr<=0x6a8) && (common_pid != 597499 && common_pid != 3313) mmap size 528384B ^C# Example with a frequent msr: # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr==IA32_SPEC_CTRL" --max-events 2 Using CPUID AuthenticAMD-25-21-0 0x48 New filter for msr:read_msr: (msr==0x48) && (common_pid != 2612129 && common_pid != 3841) 0x48 New filter for msr:write_msr: (msr==0x48) && (common_pid != 2612129 && common_pid != 3841) mmap size 528384B Looking at the vmlinux_path (8 entries long) symsrc__init: build id mismatch for vmlinux. Using /proc/kcore for kernel data Using /proc/kallsyms for symbols 0.000 Timer/2525383 msr:write_msr(msr: IA32_SPEC_CTRL, val: 6) do_trace_write_msr ([kernel.kallsyms]) do_trace_write_msr ([kernel.kallsyms]) __switch_to_xtra ([kernel.kallsyms]) __switch_to ([kernel.kallsyms]) __schedule ([kernel.kallsyms]) schedule ([kernel.kallsyms]) futex_wait_queue_me ([kernel.kallsyms]) futex_wait ([kernel.kallsyms]) do_futex ([kernel.kallsyms]) __x64_sys_futex ([kernel.kallsyms]) do_syscall_64 ([kernel.kallsyms]) entry_SYSCALL_64_after_hwframe ([kernel.kallsyms]) __futex_abstimed_wait_common64 (/usr/lib64/libpthread-2.33.so) 0.030 :0/0 msr:write_msr(msr: IA32_SPEC_CTRL, val: 2) do_trace_write_msr ([kernel.kallsyms]) do_trace_write_msr ([kernel.kallsyms]) __switch_to_xtra ([kernel.kallsyms]) __switch_to ([kernel.kallsyms]) __schedule ([kernel.kallsyms]) schedule_idle ([kernel.kallsyms]) do_idle ([kernel.kallsyms]) cpu_startup_entry ([kernel.kallsyms]) secondary_startup_64_no_verify ([kernel.kallsyms]) # Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lore.kernel.org/lkml/YkNd7Ky+vi7H2Zl2@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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‎tools/arch/x86/include/asm/msr-index.h‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,8 @@
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#define RTIT_CTL_DISRETC BIT(11)
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#define RTIT_CTL_PTW_EN BIT(12)
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#define RTIT_CTL_BRANCH_EN BIT(13)
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#define RTIT_CTL_EVENT_EN BIT(31)
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#define RTIT_CTL_NOTNT BIT_ULL(55)
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#define RTIT_CTL_MTC_RANGE_OFFSET 14
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#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
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#define RTIT_CTL_CYC_THRESH_OFFSET 19
@@ -360,11 +362,29 @@
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#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
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#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
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#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
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#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
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#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
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/* Control-flow Enforcement Technology MSRs */
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#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
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#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
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#define CET_SHSTK_EN BIT_ULL(0)
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#define CET_WRSS_EN BIT_ULL(1)
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#define CET_ENDBR_EN BIT_ULL(2)
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#define CET_LEG_IW_EN BIT_ULL(3)
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#define CET_NO_TRACK_EN BIT_ULL(4)
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#define CET_SUPPRESS_DISABLE BIT_ULL(5)
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#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
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#define CET_SUPPRESS BIT_ULL(10)
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#define CET_WAIT_ENDBR BIT_ULL(11)
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#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
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#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
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#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
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#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
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#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
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/* Hardware P state interface */
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#define MSR_PPERF 0x0000064e
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#define MSR_PERF_LIMIT_REASONS 0x0000064f

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