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drm/msm/dpu: dpu_hw_ctl.h: fix all kernel-doc warnings
Correct and add kernel-doc comments to eliminate all warnings: Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:18 cannot understand function prototype: 'enum dpu_ctl_mode_sel' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:58 struct member 'wb' not described in 'dpu_hw_intf_cfg' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:66 Incorrect use of kernel-doc format: * kickoff hw operation for Sw controlled interfaces Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:73 Incorrect use of kernel-doc format: * check if the ctl is started Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:80 Incorrect use of kernel-doc format: * kickoff prepare is in progress hw operation for sw Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:88 Incorrect use of kernel-doc format: * Clear the value of the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:96 Incorrect use of kernel-doc format: * Query the value of the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:103 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:112 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(wb_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:121 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(cwb_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:130 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(intf_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:139 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(periph_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:148 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:157 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:166 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:175 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:185 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(dsc_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:194 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(cdm_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:202 Incorrect use of kernel-doc format: * Write the value of the pending_flush_mask to hardware Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:208 Incorrect use of kernel-doc format: * Read the value of the flush register Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:215 Incorrect use of kernel-doc format: * Setup ctl_path interface config Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:223 Incorrect use of kernel-doc format: * reset ctl_path interface config Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:244 Incorrect use of kernel-doc format: * Set all blend stages to disabled Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:250 Incorrect use of kernel-doc format: * Configure layer mixer to pipe configuration Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:262 Incorrect use of kernel-doc format: * Set active pipes attached to this CTL Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:270 Incorrect use of kernel-doc format: * Set active layer mixers attached to this CTL Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member 'trigger_start' not described in 'dpu_hw_ctl_ops' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member 'is_started' not described in 'dpu_hw_ctl_ops' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member 'trigger_pending' not described in 'dpu_hw_ctl_ops' [many here] Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member 'pending_periph_flush_mask' not described in 'dpu_hw_ctl' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member 'pending_merge_3d_flush_mask' not described in 'dpu_hw_ctl' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member 'pending_dspp_flush_mask' not described in 'dpu_hw_ctl' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:327 expecting prototype for dpu_hw_ctl(). Prototype was for to_dpu_hw_ctl() instead Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/695649/ Link: https://lore.kernel.org/r/20251219184638.1813181-5-rdunlap@infradead.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
1 parent ce26953 commit 686f6aa

1 file changed

Lines changed: 53 additions & 31 deletions

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‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h‎

Lines changed: 53 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@
1212
#include "dpu_hw_sspp.h"
1313

1414
/**
15-
* dpu_ctl_mode_sel: Interface mode selection
16-
* DPU_CTL_MODE_SEL_VID: Video mode interface
17-
* DPU_CTL_MODE_SEL_CMD: Command mode interface
15+
* enum dpu_ctl_mode_sel: Interface mode selection
16+
* @DPU_CTL_MODE_SEL_VID: Video mode interface
17+
* @DPU_CTL_MODE_SEL_CMD: Command mode interface
1818
*/
1919
enum dpu_ctl_mode_sel {
2020
DPU_CTL_MODE_SEL_VID = 0,
@@ -37,6 +37,7 @@ struct dpu_hw_stage_cfg {
3737
* struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
3838
* @intf : Interface id
3939
* @intf_master: Master interface id in the dual pipe topology
40+
* @wb: Writeback mode
4041
* @mode_3d: 3d mux configuration
4142
* @merge_3d: 3d merge block used
4243
* @intf_mode_sel: Interface mode, cmd / vid
@@ -64,44 +65,45 @@ struct dpu_hw_intf_cfg {
6465
*/
6566
struct dpu_hw_ctl_ops {
6667
/**
67-
* kickoff hw operation for Sw controlled interfaces
68+
* @trigger_start: kickoff hw operation for Sw controlled interfaces
6869
* DSI cmd mode and WB interface are SW controlled
6970
* @ctx : ctl path ctx pointer
7071
*/
7172
void (*trigger_start)(struct dpu_hw_ctl *ctx);
7273

7374
/**
74-
* check if the ctl is started
75+
* @is_started: check if the ctl is started
7576
* @ctx : ctl path ctx pointer
7677
* @Return: true if started, false if stopped
7778
*/
7879
bool (*is_started)(struct dpu_hw_ctl *ctx);
7980

8081
/**
81-
* kickoff prepare is in progress hw operation for sw
82+
* @trigger_pending: kickoff prepare is in progress hw operation for sw
8283
* controlled interfaces: DSI cmd mode and WB interface
8384
* are SW controlled
8485
* @ctx : ctl path ctx pointer
8586
*/
8687
void (*trigger_pending)(struct dpu_hw_ctl *ctx);
8788

8889
/**
89-
* Clear the value of the cached pending_flush_mask
90+
* @clear_pending_flush: Clear the value of the cached pending_flush_mask
9091
* No effect on hardware.
9192
* Required to be implemented.
9293
* @ctx : ctl path ctx pointer
9394
*/
9495
void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
9596

9697
/**
97-
* Query the value of the cached pending_flush_mask
98+
* @get_pending_flush: Query the value of the cached pending_flush_mask
9899
* No effect on hardware
99100
* @ctx : ctl path ctx pointer
100101
*/
101102
u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
102103

103104
/**
104-
* OR in the given flushbits to the cached pending_flush_mask
105+
* @update_pending_flush: OR in the given flushbits to the cached
106+
* pending_flush_mask.
105107
* No effect on hardware
106108
* @ctx : ctl path ctx pointer
107109
* @flushbits : module flushmask
@@ -110,7 +112,8 @@ struct dpu_hw_ctl_ops {
110112
u32 flushbits);
111113

112114
/**
113-
* OR in the given flushbits to the cached pending_(wb_)flush_mask
115+
* @update_pending_flush_wb: OR in the given flushbits to the
116+
* cached pending_(wb_)flush_mask.
114117
* No effect on hardware
115118
* @ctx : ctl path ctx pointer
116119
* @blk : writeback block index
@@ -119,7 +122,8 @@ struct dpu_hw_ctl_ops {
119122
enum dpu_wb blk);
120123

121124
/**
122-
* OR in the given flushbits to the cached pending_(cwb_)flush_mask
125+
* @update_pending_flush_cwb: OR in the given flushbits to the
126+
* cached pending_(cwb_)flush_mask.
123127
* No effect on hardware
124128
* @ctx : ctl path ctx pointer
125129
* @blk : concurrent writeback block index
@@ -128,7 +132,8 @@ struct dpu_hw_ctl_ops {
128132
enum dpu_cwb blk);
129133

130134
/**
131-
* OR in the given flushbits to the cached pending_(intf_)flush_mask
135+
* @update_pending_flush_intf: OR in the given flushbits to the
136+
* cached pending_(intf_)flush_mask.
132137
* No effect on hardware
133138
* @ctx : ctl path ctx pointer
134139
* @blk : interface block index
@@ -137,7 +142,8 @@ struct dpu_hw_ctl_ops {
137142
enum dpu_intf blk);
138143

139144
/**
140-
* OR in the given flushbits to the cached pending_(periph_)flush_mask
145+
* @update_pending_flush_periph: OR in the given flushbits to the
146+
* cached pending_(periph_)flush_mask.
141147
* No effect on hardware
142148
* @ctx : ctl path ctx pointer
143149
* @blk : interface block index
@@ -146,7 +152,8 @@ struct dpu_hw_ctl_ops {
146152
enum dpu_intf blk);
147153

148154
/**
149-
* OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
155+
* @update_pending_flush_merge_3d: OR in the given flushbits to the
156+
* cached pending_(merge_3d_)flush_mask.
150157
* No effect on hardware
151158
* @ctx : ctl path ctx pointer
152159
* @blk : interface block index
@@ -155,7 +162,8 @@ struct dpu_hw_ctl_ops {
155162
enum dpu_merge_3d blk);
156163

157164
/**
158-
* OR in the given flushbits to the cached pending_flush_mask
165+
* @update_pending_flush_sspp: OR in the given flushbits to the
166+
* cached pending_flush_mask.
159167
* No effect on hardware
160168
* @ctx : ctl path ctx pointer
161169
* @blk : SSPP block index
@@ -164,7 +172,8 @@ struct dpu_hw_ctl_ops {
164172
enum dpu_sspp blk);
165173

166174
/**
167-
* OR in the given flushbits to the cached pending_flush_mask
175+
* @update_pending_flush_mixer: OR in the given flushbits to the
176+
* cached pending_flush_mask.
168177
* No effect on hardware
169178
* @ctx : ctl path ctx pointer
170179
* @blk : LM block index
@@ -173,7 +182,8 @@ struct dpu_hw_ctl_ops {
173182
enum dpu_lm blk);
174183

175184
/**
176-
* OR in the given flushbits to the cached pending_flush_mask
185+
* @update_pending_flush_dspp: OR in the given flushbits to the
186+
* cached pending_flush_mask.
177187
* No effect on hardware
178188
* @ctx : ctl path ctx pointer
179189
* @blk : DSPP block index
@@ -183,7 +193,8 @@ struct dpu_hw_ctl_ops {
183193
enum dpu_dspp blk, u32 dspp_sub_blk);
184194

185195
/**
186-
* OR in the given flushbits to the cached pending_(dsc_)flush_mask
196+
* @update_pending_flush_dsc: OR in the given flushbits to the
197+
* cached pending_(dsc_)flush_mask.
187198
* No effect on hardware
188199
* @ctx: ctl path ctx pointer
189200
* @blk: interface block index
@@ -192,46 +203,50 @@ struct dpu_hw_ctl_ops {
192203
enum dpu_dsc blk);
193204

194205
/**
195-
* OR in the given flushbits to the cached pending_(cdm_)flush_mask
206+
* @update_pending_flush_cdm: OR in the given flushbits to the
207+
* cached pending_(cdm_)flush_mask.
196208
* No effect on hardware
197209
* @ctx: ctl path ctx pointer
198210
* @cdm_num: idx of cdm to be flushed
199211
*/
200212
void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);
201213

202214
/**
203-
* Write the value of the pending_flush_mask to hardware
215+
* @trigger_flush: Write the value of the pending_flush_mask to hardware
204216
* @ctx : ctl path ctx pointer
205217
*/
206218
void (*trigger_flush)(struct dpu_hw_ctl *ctx);
207219

208220
/**
209-
* Read the value of the flush register
221+
* @get_flush_register: Read the value of the flush register
210222
* @ctx : ctl path ctx pointer
211223
* @Return: value of the ctl flush register.
212224
*/
213225
u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
214226

215227
/**
216-
* Setup ctl_path interface config
228+
* @setup_intf_cfg: Setup ctl_path interface config
217229
* @ctx
218230
* @cfg : interface config structure pointer
219231
*/
220232
void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
221233
struct dpu_hw_intf_cfg *cfg);
222234

223235
/**
224-
* reset ctl_path interface config
236+
* @reset_intf_cfg: reset ctl_path interface config
225237
* @ctx : ctl path ctx pointer
226238
* @cfg : interface config structure pointer
227239
*/
228240
void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
229241
struct dpu_hw_intf_cfg *cfg);
230242

243+
/**
244+
* @reset: reset function for this ctl type
245+
*/
231246
int (*reset)(struct dpu_hw_ctl *c);
232247

233-
/*
234-
* wait_reset_status - checks ctl reset status
248+
/**
249+
* @wait_reset_status: checks ctl reset status
235250
* @ctx : ctl path ctx pointer
236251
*
237252
* This function checks the ctl reset status bit.
@@ -242,39 +257,43 @@ struct dpu_hw_ctl_ops {
242257
int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
243258

244259
/**
245-
* Set all blend stages to disabled
260+
* @clear_all_blendstages: Set all blend stages to disabled
246261
* @ctx : ctl path ctx pointer
247262
*/
248263
void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
249264

250265
/**
251-
* Configure layer mixer to pipe configuration
266+
* @setup_blendstage: Configure layer mixer to pipe configuration
252267
* @ctx : ctl path ctx pointer
253268
* @lm : layer mixer enumeration
254269
* @cfg : blend stage configuration
255270
*/
256271
void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
257272
enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
258273

274+
/**
275+
* @set_active_fetch_pipes: Set active pipes attached to this CTL
276+
* @ctx: ctl path ctx pointer
277+
* @active_pipes: bitmap of enum dpu_sspp
278+
*/
259279
void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx,
260280
unsigned long *fetch_active);
261281

262282
/**
263-
* Set active pipes attached to this CTL
283+
* @set_active_pipes: Set active pipes attached to this CTL
264284
* @ctx: ctl path ctx pointer
265285
* @active_pipes: bitmap of enum dpu_sspp
266286
*/
267287
void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
268288
unsigned long *active_pipes);
269289

270290
/**
271-
* Set active layer mixers attached to this CTL
291+
* @set_active_lms: Set active layer mixers attached to this CTL
272292
* @ctx: ctl path ctx pointer
273293
* @active_lms: bitmap of enum dpu_lm
274294
*/
275295
void (*set_active_lms)(struct dpu_hw_ctl *ctx,
276296
unsigned long *active_lms);
277-
278297
};
279298

280299
/**
@@ -289,6 +308,9 @@ struct dpu_hw_ctl_ops {
289308
* @pending_intf_flush_mask: pending INTF flush
290309
* @pending_wb_flush_mask: pending WB flush
291310
* @pending_cwb_flush_mask: pending CWB flush
311+
* @pending_periph_flush_mask: pending PERIPH flush
312+
* @pending_merge_3d_flush_mask: pending MERGE 3D flush
313+
* @pending_dspp_flush_mask: pending DSPP flush
292314
* @pending_dsc_flush_mask: pending DSC flush
293315
* @pending_cdm_flush_mask: pending CDM flush
294316
* @mdss_ver: MDSS revision information
@@ -320,7 +342,7 @@ struct dpu_hw_ctl {
320342
};
321343

322344
/**
323-
* dpu_hw_ctl - convert base object dpu_hw_base to container
345+
* to_dpu_hw_ctl - convert base object dpu_hw_base to container
324346
* @hw: Pointer to base hardware block
325347
* return: Pointer to hardware block container
326348
*/

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