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KVM: nVMX: Move EVMCS1_SUPPORT_* macros to hyperv.c
Move the macros that define the set of VMCS controls that are supported by eVMCS1 from hyperv.h to hyperv.c, i.e. make them "private". The macros should never be consumed directly by KVM at-large since the "final" set of supported controls depends on guest CPUID. No functional change intended. Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20230211003534.564198-2-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Lines changed: 105 additions & 105 deletions

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‎arch/x86/kvm/vmx/hyperv.c‎

Lines changed: 105 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,111 @@
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#define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK
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/*
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* Enlightened VMCSv1 doesn't support these:
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*
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* POSTED_INTR_NV = 0x00000002,
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* GUEST_INTR_STATUS = 0x00000810,
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* APIC_ACCESS_ADDR = 0x00002014,
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* POSTED_INTR_DESC_ADDR = 0x00002016,
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* EOI_EXIT_BITMAP0 = 0x0000201c,
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* EOI_EXIT_BITMAP1 = 0x0000201e,
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* EOI_EXIT_BITMAP2 = 0x00002020,
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* EOI_EXIT_BITMAP3 = 0x00002022,
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* GUEST_PML_INDEX = 0x00000812,
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* PML_ADDRESS = 0x0000200e,
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* VM_FUNCTION_CONTROL = 0x00002018,
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* EPTP_LIST_ADDRESS = 0x00002024,
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* VMREAD_BITMAP = 0x00002026,
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* VMWRITE_BITMAP = 0x00002028,
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*
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* TSC_MULTIPLIER = 0x00002032,
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* PLE_GAP = 0x00004020,
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* PLE_WINDOW = 0x00004022,
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* VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
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*
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* Currently unsupported in KVM:
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* GUEST_IA32_RTIT_CTL = 0x00002814,
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*/
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#define EVMCS1_SUPPORTED_PINCTRL \
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(PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
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PIN_BASED_EXT_INTR_MASK | \
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PIN_BASED_NMI_EXITING | \
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PIN_BASED_VIRTUAL_NMIS)
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#define EVMCS1_SUPPORTED_EXEC_CTRL \
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(CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
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CPU_BASED_HLT_EXITING | \
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CPU_BASED_CR3_LOAD_EXITING | \
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CPU_BASED_CR3_STORE_EXITING | \
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CPU_BASED_UNCOND_IO_EXITING | \
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CPU_BASED_MOV_DR_EXITING | \
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CPU_BASED_USE_TSC_OFFSETTING | \
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CPU_BASED_MWAIT_EXITING | \
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CPU_BASED_MONITOR_EXITING | \
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CPU_BASED_INVLPG_EXITING | \
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CPU_BASED_RDPMC_EXITING | \
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CPU_BASED_INTR_WINDOW_EXITING | \
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CPU_BASED_CR8_LOAD_EXITING | \
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CPU_BASED_CR8_STORE_EXITING | \
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CPU_BASED_RDTSC_EXITING | \
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CPU_BASED_TPR_SHADOW | \
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CPU_BASED_USE_IO_BITMAPS | \
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CPU_BASED_MONITOR_TRAP_FLAG | \
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CPU_BASED_USE_MSR_BITMAPS | \
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CPU_BASED_NMI_WINDOW_EXITING | \
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CPU_BASED_PAUSE_EXITING | \
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
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#define EVMCS1_SUPPORTED_2NDEXEC \
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(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
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SECONDARY_EXEC_WBINVD_EXITING | \
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SECONDARY_EXEC_ENABLE_VPID | \
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SECONDARY_EXEC_ENABLE_EPT | \
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SECONDARY_EXEC_UNRESTRICTED_GUEST | \
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SECONDARY_EXEC_DESC | \
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SECONDARY_EXEC_ENABLE_RDTSCP | \
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SECONDARY_EXEC_ENABLE_INVPCID | \
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SECONDARY_EXEC_XSAVES | \
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SECONDARY_EXEC_RDSEED_EXITING | \
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SECONDARY_EXEC_RDRAND_EXITING | \
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SECONDARY_EXEC_TSC_SCALING | \
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SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
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SECONDARY_EXEC_PT_USE_GPA | \
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SECONDARY_EXEC_PT_CONCEAL_VMX | \
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SECONDARY_EXEC_BUS_LOCK_DETECTION | \
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SECONDARY_EXEC_NOTIFY_VM_EXITING | \
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SECONDARY_EXEC_ENCLS_EXITING)
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#define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
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#define EVMCS1_SUPPORTED_VMEXIT_CTRL \
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(VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | \
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VM_EXIT_SAVE_DEBUG_CONTROLS | \
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VM_EXIT_ACK_INTR_ON_EXIT | \
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VM_EXIT_HOST_ADDR_SPACE_SIZE | \
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VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
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VM_EXIT_SAVE_IA32_PAT | \
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VM_EXIT_LOAD_IA32_PAT | \
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VM_EXIT_SAVE_IA32_EFER | \
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VM_EXIT_LOAD_IA32_EFER | \
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VM_EXIT_CLEAR_BNDCFGS | \
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VM_EXIT_PT_CONCEAL_PIP | \
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VM_EXIT_CLEAR_IA32_RTIT_CTL)
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#define EVMCS1_SUPPORTED_VMENTRY_CTRL \
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(VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | \
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VM_ENTRY_LOAD_DEBUG_CONTROLS | \
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VM_ENTRY_IA32E_MODE | \
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VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
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VM_ENTRY_LOAD_IA32_PAT | \
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VM_ENTRY_LOAD_IA32_EFER | \
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VM_ENTRY_LOAD_BNDCFGS | \
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VM_ENTRY_PT_CONCEAL_PIP | \
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VM_ENTRY_LOAD_IA32_RTIT_CTL)
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#define EVMCS1_SUPPORTED_VMFUNC (0)
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DEFINE_STATIC_KEY_FALSE(enable_evmcs);
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#define EVMCS1_OFFSET(x) offsetof(struct hv_enlightened_vmcs, x)

‎arch/x86/kvm/vmx/hyperv.h‎

Lines changed: 0 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -22,111 +22,6 @@ DECLARE_STATIC_KEY_FALSE(enable_evmcs);
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#define KVM_EVMCS_VERSION 1
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/*
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* Enlightened VMCSv1 doesn't support these:
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*
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* POSTED_INTR_NV = 0x00000002,
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* GUEST_INTR_STATUS = 0x00000810,
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* APIC_ACCESS_ADDR = 0x00002014,
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* POSTED_INTR_DESC_ADDR = 0x00002016,
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* EOI_EXIT_BITMAP0 = 0x0000201c,
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* EOI_EXIT_BITMAP1 = 0x0000201e,
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* EOI_EXIT_BITMAP2 = 0x00002020,
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* EOI_EXIT_BITMAP3 = 0x00002022,
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* GUEST_PML_INDEX = 0x00000812,
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* PML_ADDRESS = 0x0000200e,
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* VM_FUNCTION_CONTROL = 0x00002018,
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* EPTP_LIST_ADDRESS = 0x00002024,
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* VMREAD_BITMAP = 0x00002026,
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* VMWRITE_BITMAP = 0x00002028,
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*
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* TSC_MULTIPLIER = 0x00002032,
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* PLE_GAP = 0x00004020,
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* PLE_WINDOW = 0x00004022,
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* VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
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*
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* Currently unsupported in KVM:
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* GUEST_IA32_RTIT_CTL = 0x00002814,
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*/
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#define EVMCS1_SUPPORTED_PINCTRL \
52-
(PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
53-
PIN_BASED_EXT_INTR_MASK | \
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PIN_BASED_NMI_EXITING | \
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PIN_BASED_VIRTUAL_NMIS)
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57-
#define EVMCS1_SUPPORTED_EXEC_CTRL \
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(CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
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CPU_BASED_HLT_EXITING | \
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CPU_BASED_CR3_LOAD_EXITING | \
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CPU_BASED_CR3_STORE_EXITING | \
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CPU_BASED_UNCOND_IO_EXITING | \
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CPU_BASED_MOV_DR_EXITING | \
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CPU_BASED_USE_TSC_OFFSETTING | \
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CPU_BASED_MWAIT_EXITING | \
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CPU_BASED_MONITOR_EXITING | \
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CPU_BASED_INVLPG_EXITING | \
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CPU_BASED_RDPMC_EXITING | \
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CPU_BASED_INTR_WINDOW_EXITING | \
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CPU_BASED_CR8_LOAD_EXITING | \
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CPU_BASED_CR8_STORE_EXITING | \
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CPU_BASED_RDTSC_EXITING | \
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CPU_BASED_TPR_SHADOW | \
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CPU_BASED_USE_IO_BITMAPS | \
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CPU_BASED_MONITOR_TRAP_FLAG | \
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CPU_BASED_USE_MSR_BITMAPS | \
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CPU_BASED_NMI_WINDOW_EXITING | \
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CPU_BASED_PAUSE_EXITING | \
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
80-
81-
#define EVMCS1_SUPPORTED_2NDEXEC \
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(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
83-
SECONDARY_EXEC_WBINVD_EXITING | \
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SECONDARY_EXEC_ENABLE_VPID | \
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SECONDARY_EXEC_ENABLE_EPT | \
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SECONDARY_EXEC_UNRESTRICTED_GUEST | \
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SECONDARY_EXEC_DESC | \
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SECONDARY_EXEC_ENABLE_RDTSCP | \
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SECONDARY_EXEC_ENABLE_INVPCID | \
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SECONDARY_EXEC_XSAVES | \
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SECONDARY_EXEC_RDSEED_EXITING | \
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SECONDARY_EXEC_RDRAND_EXITING | \
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SECONDARY_EXEC_TSC_SCALING | \
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SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
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SECONDARY_EXEC_PT_USE_GPA | \
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SECONDARY_EXEC_PT_CONCEAL_VMX | \
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SECONDARY_EXEC_BUS_LOCK_DETECTION | \
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SECONDARY_EXEC_NOTIFY_VM_EXITING | \
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SECONDARY_EXEC_ENCLS_EXITING)
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101-
#define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
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#define EVMCS1_SUPPORTED_VMEXIT_CTRL \
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(VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | \
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VM_EXIT_SAVE_DEBUG_CONTROLS | \
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VM_EXIT_ACK_INTR_ON_EXIT | \
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VM_EXIT_HOST_ADDR_SPACE_SIZE | \
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VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
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VM_EXIT_SAVE_IA32_PAT | \
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VM_EXIT_LOAD_IA32_PAT | \
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VM_EXIT_SAVE_IA32_EFER | \
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VM_EXIT_LOAD_IA32_EFER | \
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VM_EXIT_CLEAR_BNDCFGS | \
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VM_EXIT_PT_CONCEAL_PIP | \
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VM_EXIT_CLEAR_IA32_RTIT_CTL)
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#define EVMCS1_SUPPORTED_VMENTRY_CTRL \
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(VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | \
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VM_ENTRY_LOAD_DEBUG_CONTROLS | \
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VM_ENTRY_IA32E_MODE | \
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VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
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VM_ENTRY_LOAD_IA32_PAT | \
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VM_ENTRY_LOAD_IA32_EFER | \
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VM_ENTRY_LOAD_BNDCFGS | \
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VM_ENTRY_PT_CONCEAL_PIP | \
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VM_ENTRY_LOAD_IA32_RTIT_CTL)
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#define EVMCS1_SUPPORTED_VMFUNC (0)
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struct evmcs_field {
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u16 offset;
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u16 clean_field;

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