Skip to content

Commit 692c9b0

Browse files
mindachen1987bjorn-helgaas
mindachen1987
authored and
bjorn-helgaas
committed
PCI: microchip: Move PLDA IP register macros to pcie-plda.h
Move PLDA PCIe host controller IP registers macros to pcie-plda.h, including bridge registers and PLDA IRQ event number. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-4-minda.chen@starfivetech.com Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
1 parent 24934ee commit 692c9b0

3 files changed

Lines changed: 125 additions & 92 deletions

File tree

‎MAINTAINERS‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17224,6 +17224,7 @@ M: Daire McNamara <daire.mcnamara@microchip.com>
1722417224
L: linux-pci@vger.kernel.org
1722517225
S: Maintained
1722617226
F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml
17227+
F: drivers/pci/controller/plda/pcie-plda.h
1722717228

1722817229
PCI DRIVER FOR RENESAS R-CAR
1722917230
M: Marek Vasut <marek.vasut+renesas@gmail.com>

‎drivers/pci/controller/plda/pcie-microchip-host.c‎

Lines changed: 16 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include <linux/platform_device.h>
2020

2121
#include "../../pci.h"
22+
#include "pcie-plda.h"
2223

2324
/* Number of MSI IRQs */
2425
#define MC_MAX_NUM_MSI_IRQS 32
@@ -30,84 +31,6 @@
3031
#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
3132
#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
3233

33-
/* PCIe Bridge Phy Regs */
34-
#define PCIE_PCI_IRQ_DW0 0xa8
35-
#define MSIX_CAP_MASK BIT(31)
36-
#define NUM_MSI_MSGS_MASK GENMASK(6, 4)
37-
#define NUM_MSI_MSGS_SHIFT 4
38-
39-
#define IMASK_LOCAL 0x180
40-
#define DMA_END_ENGINE_0_MASK 0x00000000u
41-
#define DMA_END_ENGINE_0_SHIFT 0
42-
#define DMA_END_ENGINE_1_MASK 0x00000000u
43-
#define DMA_END_ENGINE_1_SHIFT 1
44-
#define DMA_ERROR_ENGINE_0_MASK 0x00000100u
45-
#define DMA_ERROR_ENGINE_0_SHIFT 8
46-
#define DMA_ERROR_ENGINE_1_MASK 0x00000200u
47-
#define DMA_ERROR_ENGINE_1_SHIFT 9
48-
#define A_ATR_EVT_POST_ERR_MASK 0x00010000u
49-
#define A_ATR_EVT_POST_ERR_SHIFT 16
50-
#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u
51-
#define A_ATR_EVT_FETCH_ERR_SHIFT 17
52-
#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u
53-
#define A_ATR_EVT_DISCARD_ERR_SHIFT 18
54-
#define A_ATR_EVT_DOORBELL_MASK 0x00000000u
55-
#define A_ATR_EVT_DOORBELL_SHIFT 19
56-
#define P_ATR_EVT_POST_ERR_MASK 0x00100000u
57-
#define P_ATR_EVT_POST_ERR_SHIFT 20
58-
#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u
59-
#define P_ATR_EVT_FETCH_ERR_SHIFT 21
60-
#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u
61-
#define P_ATR_EVT_DISCARD_ERR_SHIFT 22
62-
#define P_ATR_EVT_DOORBELL_MASK 0x00000000u
63-
#define P_ATR_EVT_DOORBELL_SHIFT 23
64-
#define PM_MSI_INT_INTA_MASK 0x01000000u
65-
#define PM_MSI_INT_INTA_SHIFT 24
66-
#define PM_MSI_INT_INTB_MASK 0x02000000u
67-
#define PM_MSI_INT_INTB_SHIFT 25
68-
#define PM_MSI_INT_INTC_MASK 0x04000000u
69-
#define PM_MSI_INT_INTC_SHIFT 26
70-
#define PM_MSI_INT_INTD_MASK 0x08000000u
71-
#define PM_MSI_INT_INTD_SHIFT 27
72-
#define PM_MSI_INT_INTX_MASK 0x0f000000u
73-
#define PM_MSI_INT_INTX_SHIFT 24
74-
#define PM_MSI_INT_MSI_MASK 0x10000000u
75-
#define PM_MSI_INT_MSI_SHIFT 28
76-
#define PM_MSI_INT_AER_EVT_MASK 0x20000000u
77-
#define PM_MSI_INT_AER_EVT_SHIFT 29
78-
#define PM_MSI_INT_EVENTS_MASK 0x40000000u
79-
#define PM_MSI_INT_EVENTS_SHIFT 30
80-
#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
81-
#define PM_MSI_INT_SYS_ERR_SHIFT 31
82-
#define NUM_LOCAL_EVENTS 15
83-
#define ISTATUS_LOCAL 0x184
84-
#define IMASK_HOST 0x188
85-
#define ISTATUS_HOST 0x18c
86-
#define IMSI_ADDR 0x190
87-
#define ISTATUS_MSI 0x194
88-
89-
/* PCIe Master table init defines */
90-
#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
91-
#define ATR0_PCIE_ATR_SIZE 0x25
92-
#define ATR0_PCIE_ATR_SIZE_SHIFT 1
93-
#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u
94-
#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u
95-
#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu
96-
#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u
97-
98-
/* PCIe AXI slave table init defines */
99-
#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
100-
#define ATR_SIZE_SHIFT 1
101-
#define ATR_IMPL_ENABLE 1
102-
#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u
103-
#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
104-
#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
105-
#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
106-
#define PCIE_TX_RX_INTERFACE 0x00000000u
107-
#define PCIE_CONFIG_INTERFACE 0x00000001u
108-
109-
#define ATR_ENTRY_SIZE 32
110-
11134
/* PCIe Controller Phy Regs */
11235
#define SEC_ERROR_EVENT_CNT 0x20
11336
#define DED_ERROR_EVENT_CNT 0x24
@@ -179,20 +102,21 @@
179102
#define EVENT_LOCAL_DMA_END_ENGINE_1 12
180103
#define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
181104
#define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14
182-
#define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15
183-
#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16
184-
#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17
185-
#define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18
186-
#define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19
187-
#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20
188-
#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21
189-
#define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22
190-
#define EVENT_LOCAL_PM_MSI_INT_INTX 23
191-
#define EVENT_LOCAL_PM_MSI_INT_MSI 24
192-
#define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25
193-
#define EVENT_LOCAL_PM_MSI_INT_EVENTS 26
194-
#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27
195-
#define NUM_EVENTS 28
105+
#define NUM_MC_EVENTS 15
106+
#define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR)
107+
#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR)
108+
#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR)
109+
#define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL)
110+
#define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR)
111+
#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR)
112+
#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR)
113+
#define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL)
114+
#define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX)
115+
#define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI)
116+
#define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT)
117+
#define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS)
118+
#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR)
119+
#define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM)
196120

197121
#define PCIE_EVENT_CAUSE(x, s) \
198122
[EVENT_PCIE_ ## x] = { __stringify(x), s }

‎drivers/pci/controller/plda/pcie-plda.h‎

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,108 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* PLDA PCIe host controller driver
4+
*/
5+
6+
#ifndef _PCIE_PLDA_H
7+
#define _PCIE_PLDA_H
8+
9+
/* PCIe Bridge Phy Regs */
10+
#define PCIE_PCI_IRQ_DW0 0xa8
11+
#define MSIX_CAP_MASK BIT(31)
12+
#define NUM_MSI_MSGS_MASK GENMASK(6, 4)
13+
#define NUM_MSI_MSGS_SHIFT 4
14+
15+
#define IMASK_LOCAL 0x180
16+
#define DMA_END_ENGINE_0_MASK 0x00000000u
17+
#define DMA_END_ENGINE_0_SHIFT 0
18+
#define DMA_END_ENGINE_1_MASK 0x00000000u
19+
#define DMA_END_ENGINE_1_SHIFT 1
20+
#define DMA_ERROR_ENGINE_0_MASK 0x00000100u
21+
#define DMA_ERROR_ENGINE_0_SHIFT 8
22+
#define DMA_ERROR_ENGINE_1_MASK 0x00000200u
23+
#define DMA_ERROR_ENGINE_1_SHIFT 9
24+
#define A_ATR_EVT_POST_ERR_MASK 0x00010000u
25+
#define A_ATR_EVT_POST_ERR_SHIFT 16
26+
#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u
27+
#define A_ATR_EVT_FETCH_ERR_SHIFT 17
28+
#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u
29+
#define A_ATR_EVT_DISCARD_ERR_SHIFT 18
30+
#define A_ATR_EVT_DOORBELL_MASK 0x00000000u
31+
#define A_ATR_EVT_DOORBELL_SHIFT 19
32+
#define P_ATR_EVT_POST_ERR_MASK 0x00100000u
33+
#define P_ATR_EVT_POST_ERR_SHIFT 20
34+
#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u
35+
#define P_ATR_EVT_FETCH_ERR_SHIFT 21
36+
#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u
37+
#define P_ATR_EVT_DISCARD_ERR_SHIFT 22
38+
#define P_ATR_EVT_DOORBELL_MASK 0x00000000u
39+
#define P_ATR_EVT_DOORBELL_SHIFT 23
40+
#define PM_MSI_INT_INTA_MASK 0x01000000u
41+
#define PM_MSI_INT_INTA_SHIFT 24
42+
#define PM_MSI_INT_INTB_MASK 0x02000000u
43+
#define PM_MSI_INT_INTB_SHIFT 25
44+
#define PM_MSI_INT_INTC_MASK 0x04000000u
45+
#define PM_MSI_INT_INTC_SHIFT 26
46+
#define PM_MSI_INT_INTD_MASK 0x08000000u
47+
#define PM_MSI_INT_INTD_SHIFT 27
48+
#define PM_MSI_INT_INTX_MASK 0x0f000000u
49+
#define PM_MSI_INT_INTX_SHIFT 24
50+
#define PM_MSI_INT_MSI_MASK 0x10000000u
51+
#define PM_MSI_INT_MSI_SHIFT 28
52+
#define PM_MSI_INT_AER_EVT_MASK 0x20000000u
53+
#define PM_MSI_INT_AER_EVT_SHIFT 29
54+
#define PM_MSI_INT_EVENTS_MASK 0x40000000u
55+
#define PM_MSI_INT_EVENTS_SHIFT 30
56+
#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
57+
#define PM_MSI_INT_SYS_ERR_SHIFT 31
58+
#define NUM_LOCAL_EVENTS 15
59+
#define ISTATUS_LOCAL 0x184
60+
#define IMASK_HOST 0x188
61+
#define ISTATUS_HOST 0x18c
62+
#define IMSI_ADDR 0x190
63+
#define ISTATUS_MSI 0x194
64+
65+
/* PCIe Master table init defines */
66+
#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
67+
#define ATR0_PCIE_ATR_SIZE 0x25
68+
#define ATR0_PCIE_ATR_SIZE_SHIFT 1
69+
#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u
70+
#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u
71+
#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu
72+
#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u
73+
74+
/* PCIe AXI slave table init defines */
75+
#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
76+
#define ATR_SIZE_SHIFT 1
77+
#define ATR_IMPL_ENABLE 1
78+
#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u
79+
#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
80+
#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
81+
#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
82+
#define PCIE_TX_RX_INTERFACE 0x00000000u
83+
#define PCIE_CONFIG_INTERFACE 0x00000001u
84+
85+
#define ATR_ENTRY_SIZE 32
86+
87+
enum plda_int_event {
88+
PLDA_AXI_POST_ERR,
89+
PLDA_AXI_FETCH_ERR,
90+
PLDA_AXI_DISCARD_ERR,
91+
PLDA_AXI_DOORBELL,
92+
PLDA_PCIE_POST_ERR,
93+
PLDA_PCIE_FETCH_ERR,
94+
PLDA_PCIE_DISCARD_ERR,
95+
PLDA_PCIE_DOORBELL,
96+
PLDA_INTX,
97+
PLDA_MSI,
98+
PLDA_AER_EVENT,
99+
PLDA_MISC_EVENTS,
100+
PLDA_SYS_ERR,
101+
PLDA_INT_EVENT_NUM
102+
};
103+
104+
#define PLDA_NUM_DMA_EVENTS 16
105+
106+
#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
107+
108+
#endif

0 commit comments

Comments
 (0)