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jernejskmchehab
jernejsk
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mchehab
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media: hantro: vp9: add support for legacy register set
Some older G2 cores uses slightly different register set for HEVC and VP9. Since vast majority of registers and logic is the same, it doesn't make sense to introduce another drivers. Add legacy_regs quirk and implement only VP9 changes for now. HEVC changes will be introduced later, if needed. Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
1 parent e67a09d commit 6a7c321

3 files changed

Lines changed: 75 additions & 17 deletions

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‎drivers/staging/media/hantro/hantro.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,7 @@ struct hantro_irq {
7474
* @reg_names: array of register range names
7575
* @num_regs: number of register range names in the array
7676
* @double_buffer: core needs double buffering
77+
* @legacy_regs: core uses legacy register set
7778
*/
7879
struct hantro_variant {
7980
unsigned int enc_offset;
@@ -96,6 +97,7 @@ struct hantro_variant {
9697
const char * const *reg_names;
9798
int num_regs;
9899
unsigned int double_buffer : 1;
100+
unsigned int legacy_regs : 1;
99101
};
100102

101103
/**

‎drivers/staging/media/hantro/hantro_g2_regs.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,13 @@
3636
#define BUS_WIDTH_256 3
3737

3838
#define g2_strm_swap G2_DEC_REG(2, 28, 0xf)
39+
#define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f)
40+
#define g2_pic_swap G2_DEC_REG(2, 22, 0x1f)
3941
#define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf)
42+
#define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f)
43+
#define g2_tab0_swap_old G2_DEC_REG(2, 12, 0x1f)
44+
#define g2_tab1_swap_old G2_DEC_REG(2, 7, 0x1f)
45+
#define g2_tab2_swap_old G2_DEC_REG(2, 2, 0x1f)
4046

4147
#define g2_mode G2_DEC_REG(3, 27, 0x1f)
4248
#define g2_compress_swap G2_DEC_REG(3, 20, 0xf)
@@ -45,6 +51,8 @@
4551
#define g2_out_dis G2_DEC_REG(3, 15, 0x1)
4652
#define g2_out_filtering_dis G2_DEC_REG(3, 14, 0x1)
4753
#define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1)
54+
#define g2_tab3_swap_old G2_DEC_REG(3, 7, 0x1f)
55+
#define g2_rscan_swap G2_DEC_REG(3, 2, 0x1f)
4856

4957
#define g2_pic_width_in_cbs G2_DEC_REG(4, 19, 0x1fff)
5058
#define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff)
@@ -58,6 +66,7 @@
5866
#define g2_tempor_mvp_e G2_DEC_REG(5, 11, 0x1)
5967
#define g2_max_cu_qpd_depth G2_DEC_REG(5, 5, 0x3f)
6068
#define g2_cu_qpd_e G2_DEC_REG(5, 4, 0x1)
69+
#define g2_pix_shift G2_DEC_REG(5, 0, 0xf)
6170

6271
#define g2_stream_len G2_DEC_REG(6, 0, 0xffffffff)
6372

@@ -80,21 +89,28 @@
8089

8190
#define g2_const_intra_e G2_DEC_REG(8, 31, 0x1)
8291
#define g2_filt_ctrl_pres G2_DEC_REG(8, 30, 0x1)
92+
#define g2_bit_depth_y G2_DEC_REG(8, 21, 0xf)
93+
#define g2_bit_depth_c G2_DEC_REG(8, 17, 0xf)
8394
#define g2_idr_pic_e G2_DEC_REG(8, 16, 0x1)
8495
#define g2_bit_depth_pcm_y G2_DEC_REG(8, 12, 0xf)
8596
#define g2_bit_depth_pcm_c G2_DEC_REG(8, 8, 0xf)
8697
#define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3)
8798
#define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3)
99+
#define g2_rs_out_bit_depth G2_DEC_REG(8, 4, 0xf)
88100
#define g2_output_8_bits G2_DEC_REG(8, 3, 0x1)
89101
#define g2_output_format G2_DEC_REG(8, 0, 0x7)
102+
#define g2_pp_pix_shift G2_DEC_REG(8, 0, 0xf)
90103

91104
#define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f)
92105
#define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f)
93106
#define g2_hdr_skip_length G2_DEC_REG(9, 0, 0x3fff)
94107

95108
#define g2_start_code_e G2_DEC_REG(10, 31, 0x1)
109+
#define g2_init_qp_old G2_DEC_REG(10, 25, 0x3f)
96110
#define g2_init_qp G2_DEC_REG(10, 24, 0x3f)
111+
#define g2_num_tile_cols_old G2_DEC_REG(10, 20, 0x1f)
97112
#define g2_num_tile_cols G2_DEC_REG(10, 19, 0x1f)
113+
#define g2_num_tile_rows_old G2_DEC_REG(10, 15, 0x1f)
98114
#define g2_num_tile_rows G2_DEC_REG(10, 14, 0x1f)
99115
#define g2_tile_e G2_DEC_REG(10, 1, 0x1)
100116
#define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1)

‎drivers/staging/media/hantro/hantro_g2_vp9_dec.c‎

Lines changed: 57 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx,
150150
dma_addr_t luma_addr, chroma_addr, mv_addr;
151151

152152
hantro_reg_write(ctx->dev, &g2_out_dis, 0);
153-
hantro_reg_write(ctx->dev, &g2_output_format, 0);
153+
if (!ctx->dev->variant->legacy_regs)
154+
hantro_reg_write(ctx->dev, &g2_output_format, 0);
154155

155156
luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
156157
hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr);
@@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx,
327328
struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge;
328329
dma_addr_t addr;
329330
unsigned short *tile_mem;
331+
unsigned int rows, cols;
330332

331333
addr = misc->dma + vp9_ctx->tile_info_offset;
332334
hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr);
@@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx,
344346

345347
fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem);
346348

349+
cols = tile_c;
350+
rows = tile_r;
347351
hantro_reg_write(ctx->dev, &g2_tile_e, 1);
348-
hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c);
349-
hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r);
350-
351352
} else {
352353
tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width);
353354
tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height);
354355

356+
cols = 1;
357+
rows = 1;
355358
hantro_reg_write(ctx->dev, &g2_tile_e, 0);
356-
hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1);
357-
hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1);
359+
}
360+
361+
if (ctx->dev->variant->legacy_regs) {
362+
hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols);
363+
hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows);
364+
} else {
365+
hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols);
366+
hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows);
358367
}
359368

360369
/* provide aux buffers even if no tiles are used */
@@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco
505514
static void
506515
config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)
507516
{
508-
hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);
509-
hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8);
517+
if (ctx->dev->variant->legacy_regs) {
518+
u8 pp_shift = 0;
519+
520+
hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth);
521+
hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth);
522+
hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth);
523+
524+
if (dec_params->bit_depth > 8)
525+
pp_shift = 16 - dec_params->bit_depth;
526+
527+
hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift);
528+
hantro_reg_write(ctx->dev, &g2_pix_shift, 0);
529+
} else {
530+
hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);
531+
hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8);
532+
}
510533
}
511534

512535
static inline bool is_lossless(const struct v4l2_vp9_quantization *quant)
@@ -784,20 +807,26 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para
784807
+ dec_params->compressed_header_size;
785808

786809
stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0);
787-
hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base);
788810

789811
tmp_addr = stream_base + headres_size;
812+
if (ctx->dev->variant->legacy_regs)
813+
hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf));
814+
else
815+
hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base);
816+
790817
start_bit = (tmp_addr & 0xf) * 8;
791818
hantro_reg_write(ctx->dev, &g2_start_bit, start_bit);
792819

793820
src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0);
794821
src_len += start_bit / 8 - headres_size;
795822
hantro_reg_write(ctx->dev, &g2_stream_len, src_len);
796823

797-
tmp_addr &= ~0xf;
798-
hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base);
799-
src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
800-
hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len);
824+
if (!ctx->dev->variant->legacy_regs) {
825+
tmp_addr &= ~0xf;
826+
hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base);
827+
src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
828+
hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len);
829+
}
801830
}
802831

803832
static void
@@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p
837866

838867
/* configure basic registers */
839868
hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE);
840-
hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf);
841-
hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf);
842-
hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf);
869+
if (!ctx->dev->variant->legacy_regs) {
870+
hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf);
871+
hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf);
872+
hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf);
873+
hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1);
874+
} else {
875+
hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f);
876+
hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10);
877+
hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10);
878+
hantro_reg_write(ctx->dev, &g2_tab0_swap_old, 0x10);
879+
hantro_reg_write(ctx->dev, &g2_tab1_swap_old, 0x10);
880+
hantro_reg_write(ctx->dev, &g2_tab2_swap_old, 0x10);
881+
hantro_reg_write(ctx->dev, &g2_tab3_swap_old, 0x10);
882+
hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10);
883+
}
843884
hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128);
844885
hantro_reg_write(ctx->dev, &g2_max_burst, 16);
845886
hantro_reg_write(ctx->dev, &g2_apf_threshold, 8);
846-
hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1);
847887
hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1);
848888
hantro_reg_write(ctx->dev, &g2_max_cb_size, 6);
849889
hantro_reg_write(ctx->dev, &g2_min_cb_size, 3);

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