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ASoC: fsl: Support micfil on i.MX943
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>: On i.MX943, the FIFO data address is changed and the bit width of CICOSR is changed. Add a new compatible string and update driver for these changes.
2 parents 65880d3 + 3927c51 commit 6b07723

3 files changed

Lines changed: 79 additions & 22 deletions

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‎Documentation/devicetree/bindings/sound/fsl,micfil.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ properties:
2525
- fsl,imx8mm-micfil
2626
- fsl,imx8mp-micfil
2727
- fsl,imx93-micfil
28+
- fsl,imx943-micfil
2829

2930
reg:
3031
maxItems: 1

‎sound/soc/fsl/fsl_micfil.c‎

Lines changed: 77 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,7 @@ struct fsl_micfil_soc_data {
8989
bool use_verid;
9090
bool volume_sx;
9191
u64 formats;
92+
int fifo_offset;
9293
};
9394

9495
static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
@@ -98,6 +99,7 @@ static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
9899
.dataline = 0xf,
99100
.formats = SNDRV_PCM_FMTBIT_S16_LE,
100101
.volume_sx = true,
102+
.fifo_offset = 0,
101103
};
102104

103105
static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
@@ -107,6 +109,7 @@ static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
107109
.dataline = 0xf,
108110
.formats = SNDRV_PCM_FMTBIT_S32_LE,
109111
.volume_sx = false,
112+
.fifo_offset = 0,
110113
};
111114

112115
static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
@@ -118,12 +121,26 @@ static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
118121
.use_edma = true,
119122
.use_verid = true,
120123
.volume_sx = false,
124+
.fifo_offset = 0,
125+
};
126+
127+
static struct fsl_micfil_soc_data fsl_micfil_imx943 = {
128+
.imx = true,
129+
.fifos = 8,
130+
.fifo_depth = 32,
131+
.dataline = 0xf,
132+
.formats = SNDRV_PCM_FMTBIT_S32_LE,
133+
.use_edma = true,
134+
.use_verid = true,
135+
.volume_sx = false,
136+
.fifo_offset = -4,
121137
};
122138

123139
static const struct of_device_id fsl_micfil_dt_ids[] = {
124140
{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
125141
{ .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
126142
{ .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
143+
{ .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 },
127144
{}
128145
};
129146
MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
@@ -793,7 +810,7 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
793810
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
794811
MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
795812
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
796-
FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
813+
FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr));
797814

798815
/* Configure CIC OSR in VADCICOSR */
799816
regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
@@ -932,24 +949,46 @@ static const struct reg_default fsl_micfil_reg_defaults[] = {
932949
{REG_MICFIL_VAD0_ZCD, 0x00000004},
933950
};
934951

952+
static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
953+
{REG_MICFIL_CTRL1, 0x00000000},
954+
{REG_MICFIL_CTRL2, 0x00000000},
955+
{REG_MICFIL_STAT, 0x00000000},
956+
{REG_MICFIL_FIFO_CTRL, 0x0000001F},
957+
{REG_MICFIL_FIFO_STAT, 0x00000000},
958+
{REG_MICFIL_DATACH0 - 0x4, 0x00000000},
959+
{REG_MICFIL_DATACH1 - 0x4, 0x00000000},
960+
{REG_MICFIL_DATACH2 - 0x4, 0x00000000},
961+
{REG_MICFIL_DATACH3 - 0x4, 0x00000000},
962+
{REG_MICFIL_DATACH4 - 0x4, 0x00000000},
963+
{REG_MICFIL_DATACH5 - 0x4, 0x00000000},
964+
{REG_MICFIL_DATACH6 - 0x4, 0x00000000},
965+
{REG_MICFIL_DATACH7 - 0x4, 0x00000000},
966+
{REG_MICFIL_DC_CTRL, 0x00000000},
967+
{REG_MICFIL_OUT_CTRL, 0x00000000},
968+
{REG_MICFIL_OUT_STAT, 0x00000000},
969+
{REG_MICFIL_VAD0_CTRL1, 0x00000000},
970+
{REG_MICFIL_VAD0_CTRL2, 0x000A0000},
971+
{REG_MICFIL_VAD0_STAT, 0x00000000},
972+
{REG_MICFIL_VAD0_SCONFIG, 0x00000000},
973+
{REG_MICFIL_VAD0_NCONFIG, 0x80000000},
974+
{REG_MICFIL_VAD0_NDATA, 0x00000000},
975+
{REG_MICFIL_VAD0_ZCD, 0x00000004},
976+
};
977+
935978
static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
936979
{
937980
struct fsl_micfil *micfil = dev_get_drvdata(dev);
981+
int ofs = micfil->soc->fifo_offset;
982+
983+
if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
984+
return true;
938985

939986
switch (reg) {
940987
case REG_MICFIL_CTRL1:
941988
case REG_MICFIL_CTRL2:
942989
case REG_MICFIL_STAT:
943990
case REG_MICFIL_FIFO_CTRL:
944991
case REG_MICFIL_FIFO_STAT:
945-
case REG_MICFIL_DATACH0:
946-
case REG_MICFIL_DATACH1:
947-
case REG_MICFIL_DATACH2:
948-
case REG_MICFIL_DATACH3:
949-
case REG_MICFIL_DATACH4:
950-
case REG_MICFIL_DATACH5:
951-
case REG_MICFIL_DATACH6:
952-
case REG_MICFIL_DATACH7:
953992
case REG_MICFIL_DC_CTRL:
954993
case REG_MICFIL_OUT_CTRL:
955994
case REG_MICFIL_OUT_STAT:
@@ -1003,17 +1042,15 @@ static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
10031042

10041043
static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
10051044
{
1045+
struct fsl_micfil *micfil = dev_get_drvdata(dev);
1046+
int ofs = micfil->soc->fifo_offset;
1047+
1048+
if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1049+
return true;
1050+
10061051
switch (reg) {
10071052
case REG_MICFIL_STAT:
10081053
case REG_MICFIL_FIFO_STAT:
1009-
case REG_MICFIL_DATACH0:
1010-
case REG_MICFIL_DATACH1:
1011-
case REG_MICFIL_DATACH2:
1012-
case REG_MICFIL_DATACH3:
1013-
case REG_MICFIL_DATACH4:
1014-
case REG_MICFIL_DATACH5:
1015-
case REG_MICFIL_DATACH6:
1016-
case REG_MICFIL_DATACH7:
10171054
case REG_MICFIL_OUT_STAT:
10181055
case REG_MICFIL_VERID:
10191056
case REG_MICFIL_PARAM:
@@ -1039,6 +1076,20 @@ static const struct regmap_config fsl_micfil_regmap_config = {
10391076
.cache_type = REGCACHE_MAPLE,
10401077
};
10411078

1079+
static const struct regmap_config fsl_micfil_regmap_config_v2 = {
1080+
.reg_bits = 32,
1081+
.reg_stride = 4,
1082+
.val_bits = 32,
1083+
1084+
.max_register = REG_MICFIL_VAD0_ZCD,
1085+
.reg_defaults = fsl_micfil_reg_defaults_v2,
1086+
.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2),
1087+
.readable_reg = fsl_micfil_readable_reg,
1088+
.volatile_reg = fsl_micfil_volatile_reg,
1089+
.writeable_reg = fsl_micfil_writeable_reg,
1090+
.cache_type = REGCACHE_MAPLE,
1091+
};
1092+
10421093
/* END OF REGMAP */
10431094

10441095
static irqreturn_t micfil_isr(int irq, void *devid)
@@ -1243,9 +1294,14 @@ static int fsl_micfil_probe(struct platform_device *pdev)
12431294
if (IS_ERR(regs))
12441295
return PTR_ERR(regs);
12451296

1246-
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1247-
regs,
1248-
&fsl_micfil_regmap_config);
1297+
if (of_device_is_compatible(np, "fsl,imx943-micfil"))
1298+
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1299+
regs,
1300+
&fsl_micfil_regmap_config_v2);
1301+
else
1302+
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1303+
regs,
1304+
&fsl_micfil_regmap_config);
12491305
if (IS_ERR(micfil->regmap)) {
12501306
dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
12511307
PTR_ERR(micfil->regmap));
@@ -1314,7 +1370,7 @@ static int fsl_micfil_probe(struct platform_device *pdev)
13141370
}
13151371

13161372
micfil->dma_params_rx.chan_name = "rx";
1317-
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
1373+
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset;
13181374
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
13191375

13201376
platform_set_drvdata(pdev, micfil);

‎sound/soc/fsl/fsl_micfil.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@
6262
#define MICFIL_QSEL_VLOW1_QUALITY 5
6363
#define MICFIL_QSEL_VLOW2_QUALITY 4
6464

65-
#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
65+
#define MICFIL_CTRL2_CICOSR GENMASK(20, 16)
6666
#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
6767

6868
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */

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