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drm/i915/gvt: Fix BDW command parser regression
On BDW new Windows driver has brought extra registers to handle for LRM/LRR command in WA ctx. Add allowed registers in cmd parser for BDW. Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Yan Zhao <yan.y.zhao@intel.com> Cc: stable@vger.kernel.org Tested-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Colin Xu <colin.xu@intel.com> Fixes: 73a37a4 ("drm/i915/gvt: filter cmds "lrr-src" and "lrr-dst" in cmd_handler") Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20210414084813.3763353-1-zhenyuw@linux.intel.com
1 parent b6a37a9 commit 6b5b2a5

1 file changed

Lines changed: 13 additions & 6 deletions

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drivers/gpu/drm/i915/gvt/cmd_parser.c

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -916,19 +916,26 @@ static int cmd_reg_handler(struct parser_exec_state *s,
916916

917917
if (!strncmp(cmd, "srm", 3) ||
918918
!strncmp(cmd, "lrm", 3)) {
919-
if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
920-
offset != 0x21f0) {
919+
if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
920+
offset == 0x21f0 ||
921+
(IS_BROADWELL(gvt->gt->i915) &&
922+
offset == i915_mmio_reg_offset(INSTPM)))
923+
return 0;
924+
else {
921925
gvt_vgpu_err("%s access to register (%x)\n",
922926
cmd, offset);
923927
return -EPERM;
924-
} else
925-
return 0;
928+
}
926929
}
927930

928931
if (!strncmp(cmd, "lrr-src", 7) ||
929932
!strncmp(cmd, "lrr-dst", 7)) {
930-
gvt_vgpu_err("not allowed cmd %s\n", cmd);
931-
return -EPERM;
933+
if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
934+
return 0;
935+
else {
936+
gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
937+
return -EPERM;
938+
}
932939
}
933940

934941
if (!strncmp(cmd, "pipe_ctrl", 9)) {

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