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clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 parent b7fd5d1 commit 6bab5da

1 file changed

Lines changed: 21 additions & 21 deletions

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‎drivers/clk/qcom/gcc-mdm9615.c‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = {
207207
.hw.init = &(struct clk_init_data){
208208
.name = "gsbi1_uart_src",
209209
.parent_names = gcc_cxo_pll8,
210-
.num_parents = 2,
210+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
211211
.ops = &clk_rcg_ops,
212212
.flags = CLK_SET_PARENT_GATE,
213213
},
@@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = {
258258
.hw.init = &(struct clk_init_data){
259259
.name = "gsbi2_uart_src",
260260
.parent_names = gcc_cxo_pll8,
261-
.num_parents = 2,
261+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
262262
.ops = &clk_rcg_ops,
263263
.flags = CLK_SET_PARENT_GATE,
264264
},
@@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = {
309309
.hw.init = &(struct clk_init_data){
310310
.name = "gsbi3_uart_src",
311311
.parent_names = gcc_cxo_pll8,
312-
.num_parents = 2,
312+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
313313
.ops = &clk_rcg_ops,
314314
.flags = CLK_SET_PARENT_GATE,
315315
},
@@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = {
360360
.hw.init = &(struct clk_init_data){
361361
.name = "gsbi4_uart_src",
362362
.parent_names = gcc_cxo_pll8,
363-
.num_parents = 2,
363+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
364364
.ops = &clk_rcg_ops,
365365
.flags = CLK_SET_PARENT_GATE,
366366
},
@@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = {
411411
.hw.init = &(struct clk_init_data){
412412
.name = "gsbi5_uart_src",
413413
.parent_names = gcc_cxo_pll8,
414-
.num_parents = 2,
414+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
415415
.ops = &clk_rcg_ops,
416416
.flags = CLK_SET_PARENT_GATE,
417417
},
@@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = {
474474
.hw.init = &(struct clk_init_data){
475475
.name = "gsbi1_qup_src",
476476
.parent_names = gcc_cxo_pll8,
477-
.num_parents = 2,
477+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
478478
.ops = &clk_rcg_ops,
479479
.flags = CLK_SET_PARENT_GATE,
480480
},
@@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = {
523523
.hw.init = &(struct clk_init_data){
524524
.name = "gsbi2_qup_src",
525525
.parent_names = gcc_cxo_pll8,
526-
.num_parents = 2,
526+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
527527
.ops = &clk_rcg_ops,
528528
.flags = CLK_SET_PARENT_GATE,
529529
},
@@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = {
572572
.hw.init = &(struct clk_init_data){
573573
.name = "gsbi3_qup_src",
574574
.parent_names = gcc_cxo_pll8,
575-
.num_parents = 2,
575+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
576576
.ops = &clk_rcg_ops,
577577
.flags = CLK_SET_PARENT_GATE,
578578
},
@@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = {
621621
.hw.init = &(struct clk_init_data){
622622
.name = "gsbi4_qup_src",
623623
.parent_names = gcc_cxo_pll8,
624-
.num_parents = 2,
624+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
625625
.ops = &clk_rcg_ops,
626626
.flags = CLK_SET_PARENT_GATE,
627627
},
@@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = {
670670
.hw.init = &(struct clk_init_data){
671671
.name = "gsbi5_qup_src",
672672
.parent_names = gcc_cxo_pll8,
673-
.num_parents = 2,
673+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
674674
.ops = &clk_rcg_ops,
675675
.flags = CLK_SET_PARENT_GATE,
676676
},
@@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = {
725725
.hw.init = &(struct clk_init_data){
726726
.name = "gp0_src",
727727
.parent_names = gcc_cxo,
728-
.num_parents = 1,
728+
.num_parents = ARRAY_SIZE(gcc_cxo),
729729
.ops = &clk_rcg_ops,
730730
.flags = CLK_SET_PARENT_GATE,
731731
},
@@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = {
774774
.hw.init = &(struct clk_init_data){
775775
.name = "gp1_src",
776776
.parent_names = gcc_cxo,
777-
.num_parents = 1,
777+
.num_parents = ARRAY_SIZE(gcc_cxo),
778778
.ops = &clk_rcg_ops,
779779
.flags = CLK_SET_RATE_GATE,
780780
},
@@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = {
823823
.hw.init = &(struct clk_init_data){
824824
.name = "gp2_src",
825825
.parent_names = gcc_cxo,
826-
.num_parents = 1,
826+
.num_parents = ARRAY_SIZE(gcc_cxo),
827827
.ops = &clk_rcg_ops,
828828
.flags = CLK_SET_RATE_GATE,
829829
},
@@ -875,7 +875,7 @@ static struct clk_rcg prng_src = {
875875
.hw.init = &(struct clk_init_data){
876876
.name = "prng_src",
877877
.parent_names = gcc_cxo_pll8,
878-
.num_parents = 2,
878+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
879879
.ops = &clk_rcg_ops,
880880
},
881881
},
@@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = {
937937
.hw.init = &(struct clk_init_data){
938938
.name = "sdc1_src",
939939
.parent_names = gcc_cxo_pll8,
940-
.num_parents = 2,
940+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
941941
.ops = &clk_rcg_ops,
942942
},
943943
}
@@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = {
985985
.hw.init = &(struct clk_init_data){
986986
.name = "sdc2_src",
987987
.parent_names = gcc_cxo_pll8,
988-
.num_parents = 2,
988+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
989989
.ops = &clk_rcg_ops,
990990
},
991991
}
@@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
10381038
.hw.init = &(struct clk_init_data){
10391039
.name = "usb_hs1_xcvr_src",
10401040
.parent_names = gcc_cxo_pll8,
1041-
.num_parents = 2,
1041+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
10421042
.ops = &clk_rcg_ops,
10431043
.flags = CLK_SET_RATE_GATE,
10441044
},
@@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
10871087
.hw.init = &(struct clk_init_data){
10881088
.name = "usb_hsic_xcvr_fs_src",
10891089
.parent_names = gcc_cxo_pll8,
1090-
.num_parents = 2,
1090+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
10911091
.ops = &clk_rcg_ops,
10921092
.flags = CLK_SET_RATE_GATE,
10931093
},
@@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = {
11421142
.hw.init = &(struct clk_init_data){
11431143
.name = "usb_hs1_system_src",
11441144
.parent_names = gcc_cxo_pll8,
1145-
.num_parents = 2,
1145+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
11461146
.ops = &clk_rcg_ops,
11471147
.flags = CLK_SET_RATE_GATE,
11481148
},
@@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = {
11971197
.hw.init = &(struct clk_init_data){
11981198
.name = "usb_hsic_system_src",
11991199
.parent_names = gcc_cxo_pll8,
1200-
.num_parents = 2,
1200+
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
12011201
.ops = &clk_rcg_ops,
12021202
.flags = CLK_SET_RATE_GATE,
12031203
},
@@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
12521252
.hw.init = &(struct clk_init_data){
12531253
.name = "usb_hsic_hsic_src",
12541254
.parent_names = gcc_cxo_pll14,
1255-
.num_parents = 2,
1255+
.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
12561256
.ops = &clk_rcg_ops,
12571257
.flags = CLK_SET_RATE_GATE,
12581258
},

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