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Rahi374pinchartl
Rahi374
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pinchartl
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media: rkisp1: Fix endianness on raw streams on i.MX8MP
The i.MX8MP has extra register fields in the memory interface control register for setting the output format, which work with the output alignment format register for byte-swapping and LSB/MSB alignment. With processed and 8-bit raw streams, it doesn't cause any problems to not set these, but with raw streams of higher bit depth the endianness is swapped and the data is not aligned properly. Add support for setting these registers and plumb them in to fix this. While at it, reflow a comment related to the forced configuration update. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
1 parent 0a593f7 commit 6c14435

2 files changed

Lines changed: 85 additions & 12 deletions

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‎drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c‎

Lines changed: 76 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -48,14 +48,17 @@ enum rkisp1_plane {
4848
* @fmt_type: helper filed for pixel format
4949
* @uv_swap: if cb cr swapped, for yuv
5050
* @yc_swap: if y and cb/cr swapped, for yuv
51+
* @byte_swap: if byte pairs are swapped, for raw
5152
* @write_format: defines how YCbCr self picture data is written to memory
52-
* @output_format: defines sp output format
53+
* @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for
54+
* the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path)
5355
* @mbus: the mbus code on the src resizer pad that matches the pixel format
5456
*/
5557
struct rkisp1_capture_fmt_cfg {
5658
u32 fourcc;
5759
u32 uv_swap : 1;
5860
u32 yc_swap : 1;
61+
u32 byte_swap : 1;
5962
u32 write_format;
6063
u32 output_format;
6164
u32 mbus;
@@ -96,131 +99,166 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
9699
.fourcc = V4L2_PIX_FMT_YUYV,
97100
.uv_swap = 0,
98101
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
102+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
99103
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
100104
}, {
101105
.fourcc = V4L2_PIX_FMT_UYVY,
102106
.uv_swap = 0,
103107
.yc_swap = 1,
104108
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
109+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
105110
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
106111
}, {
107112
.fourcc = V4L2_PIX_FMT_YUV422P,
108113
.uv_swap = 0,
109114
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
115+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
110116
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
111117
}, {
112118
.fourcc = V4L2_PIX_FMT_NV16,
113119
.uv_swap = 0,
114120
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
121+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
115122
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
116123
}, {
117124
.fourcc = V4L2_PIX_FMT_NV61,
118125
.uv_swap = 1,
119126
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
127+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
120128
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
121129
}, {
122130
.fourcc = V4L2_PIX_FMT_NV16M,
123131
.uv_swap = 0,
124132
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
133+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
125134
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
126135
}, {
127136
.fourcc = V4L2_PIX_FMT_NV61M,
128137
.uv_swap = 1,
129138
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
139+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
130140
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
131141
}, {
132142
.fourcc = V4L2_PIX_FMT_YVU422M,
133143
.uv_swap = 1,
134144
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
145+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
135146
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
136147
},
137148
/* yuv400 */
138149
{
139150
.fourcc = V4L2_PIX_FMT_GREY,
140151
.uv_swap = 0,
141152
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
153+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400,
142154
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
143155
},
144156
/* yuv420 */
145157
{
146158
.fourcc = V4L2_PIX_FMT_NV21,
147159
.uv_swap = 1,
148160
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
161+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
149162
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
150163
}, {
151164
.fourcc = V4L2_PIX_FMT_NV12,
152165
.uv_swap = 0,
153166
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
167+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
154168
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
155169
}, {
156170
.fourcc = V4L2_PIX_FMT_NV21M,
157171
.uv_swap = 1,
158172
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
173+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
159174
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
160175
}, {
161176
.fourcc = V4L2_PIX_FMT_NV12M,
162177
.uv_swap = 0,
163178
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
179+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
164180
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
165181
}, {
166182
.fourcc = V4L2_PIX_FMT_YUV420,
167183
.uv_swap = 0,
168184
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
185+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
169186
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
170187
}, {
171188
.fourcc = V4L2_PIX_FMT_YVU420,
172189
.uv_swap = 1,
173190
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
191+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
174192
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
175193
},
176194
/* raw */
177195
{
178196
.fourcc = V4L2_PIX_FMT_SRGGB8,
179197
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
198+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
180199
.mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
181200
}, {
182201
.fourcc = V4L2_PIX_FMT_SGRBG8,
183202
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
203+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
184204
.mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
185205
}, {
186206
.fourcc = V4L2_PIX_FMT_SGBRG8,
187207
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
208+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
188209
.mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
189210
}, {
190211
.fourcc = V4L2_PIX_FMT_SBGGR8,
191212
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
213+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
192214
.mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
193215
}, {
194216
.fourcc = V4L2_PIX_FMT_SRGGB10,
217+
.byte_swap = 1,
195218
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
219+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
196220
.mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
197221
}, {
198222
.fourcc = V4L2_PIX_FMT_SGRBG10,
223+
.byte_swap = 1,
199224
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
225+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
200226
.mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
201227
}, {
202228
.fourcc = V4L2_PIX_FMT_SGBRG10,
229+
.byte_swap = 1,
203230
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
231+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
204232
.mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
205233
}, {
206234
.fourcc = V4L2_PIX_FMT_SBGGR10,
235+
.byte_swap = 1,
207236
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
237+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
208238
.mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
209239
}, {
210240
.fourcc = V4L2_PIX_FMT_SRGGB12,
241+
.byte_swap = 1,
211242
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
243+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
212244
.mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
213245
}, {
214246
.fourcc = V4L2_PIX_FMT_SGRBG12,
247+
.byte_swap = 1,
215248
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
249+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
216250
.mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
217251
}, {
218252
.fourcc = V4L2_PIX_FMT_SGBRG12,
253+
.byte_swap = 1,
219254
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
255+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
220256
.mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
221257
}, {
222258
.fourcc = V4L2_PIX_FMT_SBGGR12,
259+
.byte_swap = 1,
223260
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
261+
.output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
224262
.mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
225263
},
226264
};
@@ -484,11 +522,16 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
484522
*/
485523
if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
486524
reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
487-
if (cap->pix.cfg->yc_swap)
525+
if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap)
488526
reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
489527
else
490528
reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
529+
530+
reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT;
491531
rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
532+
533+
rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
534+
cap->pix.cfg->output_format);
492535
}
493536

494537
rkisp1_mi_config_ctrl(cap);
@@ -951,19 +994,40 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
951994
spin_lock_irq(&cap->buf.lock);
952995
rkisp1_set_next_buf(cap);
953996
cap->ops->enable(cap);
954-
/* It's safe to configure ACTIVE and SHADOW registers for the
955-
* first stream. While when the second is starting, do NOT
956-
* force update because it also updates the first one.
997+
998+
/*
999+
* It's safe to configure ACTIVE and SHADOW registers for the first
1000+
* stream. While when the second is starting, do NOT force update
1001+
* because it also updates the first one.
9571002
*
958-
* The latter case would drop one more buffer(that is 2) since
959-
* there's no buffer in a shadow register when the second FE received.
960-
* This's also required because the second FE maybe corrupt
961-
* especially when run at 120fps.
1003+
* The latter case would drop one more buffer(that is 2) since there's
1004+
* no buffer in a shadow register when the second FE received. This's
1005+
* also required because the second FE maybe corrupt especially when
1006+
* run at 120fps.
9621007
*/
9631008
if (!has_self_path || !other->is_streaming) {
964-
/* force cfg update */
965-
rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
966-
RKISP1_CIF_MI_INIT_SOFT_UPD);
1009+
u32 reg;
1010+
1011+
/*
1012+
* Force cfg update.
1013+
*
1014+
* The ISP8000 (implementing the MAIN_STRIDE feature) as a
1015+
* mp_output_format field in the CIF_MI_INIT register that must
1016+
* be preserved. It can be read back, but it is not clear what
1017+
* other register bits will return. Mask them out.
1018+
*
1019+
* On Rockchip platforms, the CIF_MI_INIT register is marked as
1020+
* write-only and reads as zeros. We can skip reading it.
1021+
*/
1022+
if (rkisp1_has_feature(rkisp1, MAIN_STRIDE))
1023+
reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT)
1024+
& RKISP1_CIF_MI_INIT_MP_OUTPUT_MASK;
1025+
else
1026+
reg = 0;
1027+
1028+
reg |= RKISP1_CIF_MI_INIT_SOFT_UPD;
1029+
rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg);
1030+
9671031
rkisp1_set_next_buf(cap);
9681032
}
9691033
spin_unlock_irq(&cap->buf.lock);

‎drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,15 @@
144144
/* MI_INIT */
145145
#define RKISP1_CIF_MI_INIT_SKIP BIT(2)
146146
#define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
147+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5)
148+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5)
149+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5)
150+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5)
151+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5)
152+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5)
153+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5)
154+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5)
155+
#define RKISP1_CIF_MI_INIT_MP_OUTPUT_MASK (15 << 5)
147156

148157
/* MI_CTRL_SHD */
149158
#define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)

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