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danvetdanvet
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Merge tag 'drm-etnaviv-next-2024-06-28' of https://git.pengutronix.de/git/lst/linux into drm-next
- fix i.MX8MP NPU clock gating - workaround FE register cdc issues on some cores - fix DMA sync handling for cached buffers - fix job timeout handling - keep TS enabled on MMUv2 cores for improved performance Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Lucas Stach <l.stach@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/e8b91e2f18e6eaa722569dd21f559009064b1730.camel@pengutronix.de
2 parents 3ccf1b8 + 704d3d6 commit 6cab3e2

10 files changed

Lines changed: 238 additions & 92 deletions

File tree

‎drivers/gpu/drm/etnaviv/cmdstream.xml.h‎

Lines changed: 48 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,11 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
88
git clone git://0x04.net/rules-ng-ng
99
1010
The rules-ng-ng source files this header was generated from are:
11-
- cmdstream.xml ( 14094 bytes, from 2016-11-11 06:55:14)
12-
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
13-
- common.xml ( 23344 bytes, from 2016-11-10 15:14:07)
11+
- cmdstream.xml ( 16933 bytes, from 2023-12-11 15:50:17)
12+
- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
13+
- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
1414
15-
Copyright (C) 2012-2016 by the following authors:
15+
Copyright (C) 2012-2023 by the following authors:
1616
- Wladimir J. van der Laan <laanwj@gmail.com>
1717
- Christian Gmeiner <christian.gmeiner@gmail.com>
1818
- Lucas Stach <l.stach@pengutronix.de>
@@ -52,6 +52,9 @@ DEALINGS IN THE SOFTWARE.
5252
#define FE_OPCODE_RETURN 0x0000000b
5353
#define FE_OPCODE_DRAW_INSTANCED 0x0000000c
5454
#define FE_OPCODE_CHIP_SELECT 0x0000000d
55+
#define FE_OPCODE_WAIT_FENCE 0x0000000f
56+
#define FE_OPCODE_DRAW_INDIRECT 0x00000010
57+
#define FE_OPCODE_SNAP_PAGES 0x00000013
5558
#define PRIMITIVE_TYPE_POINTS 0x00000001
5659
#define PRIMITIVE_TYPE_LINES 0x00000002
5760
#define PRIMITIVE_TYPE_LINE_STRIP 0x00000003
@@ -192,6 +195,9 @@ DEALINGS IN THE SOFTWARE.
192195
#define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00
193196
#define VIV_FE_STALL_TOKEN_TO__SHIFT 8
194197
#define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
198+
#define VIV_FE_STALL_TOKEN_UNK28__MASK 0x30000000
199+
#define VIV_FE_STALL_TOKEN_UNK28__SHIFT 28
200+
#define VIV_FE_STALL_TOKEN_UNK28(x) (((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK)
195201

196202
#define VIV_FE_CALL 0x00000000
197203

@@ -266,5 +272,43 @@ DEALINGS IN THE SOFTWARE.
266272
#define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT 0
267273
#define VIV_FE_DRAW_INSTANCED_START_INDEX(x) (((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK)
268274

275+
#define VIV_FE_WAIT_FENCE 0x00000000
276+
277+
#define VIV_FE_WAIT_FENCE_HEADER 0x00000000
278+
#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK 0xf8000000
279+
#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT 27
280+
#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE 0x78000000
281+
#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK 0x00030000
282+
#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT 16
283+
#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK)
284+
#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK 0x0000ffff
285+
#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT 0
286+
#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK)
287+
288+
#define VIV_FE_WAIT_FENCE_ADDRESS 0x00000004
289+
290+
#define VIV_FE_DRAW_INDIRECT 0x00000000
291+
292+
#define VIV_FE_DRAW_INDIRECT_HEADER 0x00000000
293+
#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK 0xf8000000
294+
#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT 27
295+
#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT 0x80000000
296+
#define VIV_FE_DRAW_INDIRECT_HEADER_INDEXED 0x00000100
297+
#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK 0x0000000f
298+
#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT 0
299+
#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK)
300+
301+
#define VIV_FE_DRAW_INDIRECT_ADDRESS 0x00000004
302+
303+
#define VIV_FE_SNAP_PAGES 0x00000000
304+
305+
#define VIV_FE_SNAP_PAGES_HEADER 0x00000000
306+
#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK 0xf8000000
307+
#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT 27
308+
#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES 0x98000000
309+
#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK 0x0000001f
310+
#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT 0
311+
#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x) (((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK)
312+
269313

270314
#endif /* CMDSTREAM_XML */

‎drivers/gpu/drm/etnaviv/common.xml.h‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,12 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
88
git clone git://0x04.net/rules-ng-ng
99
1010
The rules-ng-ng source files this header was generated from are:
11-
- texdesc_3d.xml ( 3183 bytes, from 2017-12-18 16:51:59)
12-
- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
13-
- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
14-
- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
11+
- texdesc_3d.xml ( 3183 bytes, from 2022-11-18 09:38:25)
12+
- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
13+
- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
14+
- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
1515
16-
Copyright (C) 2012-2018 by the following authors:
16+
Copyright (C) 2012-2023 by the following authors:
1717
- Wladimir J. van der Laan <laanwj@gmail.com>
1818
- Christian Gmeiner <christian.gmeiner@gmail.com>
1919
- Lucas Stach <l.stach@pengutronix.de>
@@ -65,6 +65,7 @@ DEALINGS IN THE SOFTWARE.
6565
#define chipModel_GC520 0x00000520
6666
#define chipModel_GC530 0x00000530
6767
#define chipModel_GC600 0x00000600
68+
#define chipModel_GC620 0x00000620
6869
#define chipModel_GC700 0x00000700
6970
#define chipModel_GC800 0x00000800
7071
#define chipModel_GC860 0x00000860
@@ -481,5 +482,6 @@ DEALINGS IN THE SOFTWARE.
481482
#define chipMinorFeatures11_NN_INTERLEVE8 0x00000008
482483
#define chipMinorFeatures11_TP_REORDER 0x00000010
483484
#define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020
485+
#define chipMinorFeatures12_G2D_DEC400EX 0x00000020
484486

485487
#endif /* COMMON_XML */

‎drivers/gpu/drm/etnaviv/etnaviv_dump.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -159,8 +159,7 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit)
159159
file_size += sizeof(*iter.hdr) * n_obj;
160160

161161
/* Allocate the file in vmalloc memory, it's likely to be big */
162-
iter.start = __vmalloc(file_size, GFP_KERNEL | __GFP_NOWARN |
163-
__GFP_NORETRY);
162+
iter.start = __vmalloc(file_size, GFP_NOWAIT);
164163
if (!iter.start) {
165164
mutex_unlock(&submit->mmu_context->lock);
166165
dev_warn(gpu->dev, "failed to allocate devcoredump file\n");
@@ -230,5 +229,5 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit)
230229

231230
etnaviv_core_dump_header(&iter, ETDUMP_BUF_END, iter.data);
232231

233-
dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_KERNEL);
232+
dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_NOWAIT);
234233
}

‎drivers/gpu/drm/etnaviv/etnaviv_gem.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -355,9 +355,11 @@ static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj)
355355

356356
static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)
357357
{
358-
if (op & ETNA_PREP_READ)
358+
op &= ETNA_PREP_READ | ETNA_PREP_WRITE;
359+
360+
if (op == ETNA_PREP_READ)
359361
return DMA_FROM_DEVICE;
360-
else if (op & ETNA_PREP_WRITE)
362+
else if (op == ETNA_PREP_WRITE)
361363
return DMA_TO_DEVICE;
362364
else
363365
return DMA_BIDIRECTIONAL;

‎drivers/gpu/drm/etnaviv/etnaviv_gpu.c‎

Lines changed: 47 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -172,10 +172,12 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
172172
return 0;
173173
}
174174

175+
static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
176+
{
177+
return gpu->identity.model == model &&
178+
gpu->identity.revision == revision;
179+
}
175180

176-
#define etnaviv_is_model_rev(gpu, mod, rev) \
177-
((gpu)->identity.model == chipModel_##mod && \
178-
(gpu)->identity.revision == rev)
179181
#define etnaviv_field(val, field) \
180182
(((val) & field##__MASK) >> field##__SHIFT)
181183

@@ -281,7 +283,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
281283

282284
switch (gpu->identity.instruction_count) {
283285
case 0:
284-
if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
286+
if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
285287
gpu->identity.model == chipModel_GC880)
286288
gpu->identity.instruction_count = 512;
287289
else
@@ -315,17 +317,17 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
315317
* For some cores, two varyings are consumed for position, so the
316318
* maximum varying count needs to be reduced by one.
317319
*/
318-
if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319-
etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320-
etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321-
etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322-
etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323-
etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324-
etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325-
etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326-
etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327-
etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328-
etnaviv_is_model_rev(gpu, GC880, 0x5106))
320+
if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
321+
etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
322+
etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
323+
etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
324+
etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
325+
etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
326+
etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
327+
etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
328+
etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
329+
etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
330+
etnaviv_is_model_rev(gpu, 0x880, 0x5106))
329331
gpu->identity.varyings_count -= 1;
330332
}
331333

@@ -351,7 +353,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
351353
* Reading these two registers on GC600 rev 0x19 result in a
352354
* unhandled fault: external abort on non-linefetch
353355
*/
354-
if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
356+
if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
355357
gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356358
gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357359
}
@@ -368,7 +370,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
368370
}
369371

370372
/* Another special case */
371-
if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
373+
if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
372374
u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373375

374376
if (chipDate == 0x20080814 && chipTime == 0x12051100) {
@@ -387,15 +389,15 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
387389
* Fix model/rev here, so all other places can refer to this
388390
* core by its real identity.
389391
*/
390-
if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
392+
if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
391393
gpu->identity.model = chipModel_GC3000;
392394
gpu->identity.revision &= 0xffff;
393395
}
394396

395-
if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
397+
if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
396398
gpu->identity.eco_id = 1;
397399

398-
if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
400+
if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
399401
gpu->identity.eco_id = 1;
400402
}
401403

@@ -641,17 +643,23 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
641643
pmc |= BIT(15); /* Unknown bit */
642644

643645
/* Disable TX clock gating on affected core revisions. */
644-
if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
645-
etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
646-
etnaviv_is_model_rev(gpu, GC7000, 0x6202) ||
647-
etnaviv_is_model_rev(gpu, GC7000, 0x6203))
646+
if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
647+
etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
648+
etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||
649+
etnaviv_is_model_rev(gpu, 0x7000, 0x6203))
648650
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
649651

650652
/* Disable SE and RA clock gating on affected core revisions. */
651-
if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
653+
if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
652654
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
653655
VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
654656

657+
/* Disable SH_EU clock gating on affected core revisions. */
658+
if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||
659+
etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||
660+
etnaviv_is_model_rev(gpu, 0x9200, 0x6304))
661+
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
662+
655663
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
656664
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
657665

@@ -701,14 +709,14 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
701709
*/
702710
u32 pulse_eater = 0x01590880;
703711

704-
if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
705-
etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
712+
if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
713+
etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
706714
pulse_eater |= BIT(23);
707715

708716
}
709717

710-
if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
711-
etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
718+
if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
719+
etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
712720
pulse_eater &= ~BIT(16);
713721
pulse_eater |= BIT(17);
714722
}
@@ -729,8 +737,8 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
729737
WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
730738
gpu->state == ETNA_GPU_STATE_RESET));
731739

732-
if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
733-
etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
740+
if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
741+
etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
734742
gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
735743
u32 mc_memory_debug;
736744

@@ -756,7 +764,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
756764
VIVS_HI_AXI_CONFIG_ARCACHE(2));
757765

758766
/* GC2000 rev 5108 needs a special bus config */
759-
if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
767+
if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
760768
u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
761769
bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
762770
VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
@@ -855,12 +863,15 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
855863
*
856864
* On MC1.0 cores the linear window offset is ignored by the TS engine,
857865
* leading to inconsistent memory views. Avoid using the offset on those
858-
* cores if possible, otherwise disable the TS feature.
866+
* cores if possible, otherwise disable the TS feature. MMUv2 doesn't
867+
* expose this issue, as all TS accesses are MMU translated, so the
868+
* linear window offset won't be used.
859869
*/
860870
cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
861871

862872
if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
863-
(gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
873+
(gpu->identity.minor_features0 & chipMinorFeatures0_MC20) ||
874+
(gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) {
864875
if (cmdbuf_paddr >= SZ_2G)
865876
priv->mmu_global->memory_base = SZ_2G;
866877
else
@@ -1537,6 +1548,7 @@ static irqreturn_t irq_handler(int irq, void *data)
15371548
u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
15381549

15391550
if (intr != 0) {
1551+
ktime_t now = ktime_get();
15401552
int event;
15411553

15421554
pm_runtime_mark_last_busy(gpu->dev);
@@ -1586,7 +1598,7 @@ static irqreturn_t irq_handler(int irq, void *data)
15861598
*/
15871599
if (fence_after(fence->seqno, gpu->completed_fence))
15881600
gpu->completed_fence = fence->seqno;
1589-
dma_fence_signal(fence);
1601+
dma_fence_signal_timestamp(fence, now);
15901602

15911603
event_free(gpu, event);
15921604
}
@@ -1975,7 +1987,6 @@ static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
19751987
struct platform_driver etnaviv_gpu_driver = {
19761988
.driver = {
19771989
.name = "etnaviv-gpu",
1978-
.owner = THIS_MODULE,
19791990
.pm = pm_ptr(&etnaviv_gpu_pm_ops),
19801991
.of_match_table = etnaviv_gpu_match,
19811992
},

‎drivers/gpu/drm/etnaviv/etnaviv_gpu.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include "etnaviv_mmu.h"
1212
#include "etnaviv_drv.h"
1313
#include "common.xml.h"
14+
#include "state.xml.h"
1415

1516
struct etnaviv_gem_submit;
1617
struct etnaviv_vram_mapping;
@@ -170,6 +171,13 @@ static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
170171

171172
static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
172173
{
174+
/* On some variants, such as the GC7000r6009, some FE registers
175+
* need two reads to be consistent. Do that extra read here and
176+
* throw away the result.
177+
*/
178+
if (reg >= VIVS_FE_DMA_STATUS && reg <= VIVS_FE_AUTO_FLUSH)
179+
readl(gpu->mmio + reg);
180+
173181
return readl(gpu->mmio + reg);
174182
}
175183

‎drivers/gpu/drm/etnaviv/etnaviv_sched.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,6 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job
3838
u32 dma_addr;
3939
int change;
4040

41-
/* block scheduler */
42-
drm_sched_stop(&gpu->sched, sched_job);
43-
4441
/*
4542
* If the GPU managed to complete this jobs fence, the timout is
4643
* spurious. Bail out.
@@ -63,6 +60,9 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job
6360
goto out_no_timeout;
6461
}
6562

63+
/* block scheduler */
64+
drm_sched_stop(&gpu->sched, sched_job);
65+
6666
if(sched_job)
6767
drm_sched_increase_karma(sched_job);
6868

@@ -76,8 +76,7 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job
7676
return DRM_GPU_SCHED_STAT_NOMINAL;
7777

7878
out_no_timeout:
79-
/* restart scheduler after GPU is usable again */
80-
drm_sched_start(&gpu->sched, true);
79+
list_add(&sched_job->list, &sched_job->sched->pending_list);
8180
return DRM_GPU_SCHED_STAT_NOMINAL;
8281
}
8382

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