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ZideChen0Peter Zijlstra
ZideChen0
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Peter Zijlstra
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perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids
DMR supports IMH PMON units for PCU, UBox, iMC, and CXL: - PCU and UBox are same with SPR. - iMC is similar to SPR but uses different offsets for fixed registers. - CXL introduces a new port_enable field and changes the position of the threshold field. DMR also introduces additional PMON units: SCA, HAMVF, D2D_ULA, UBR, PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6. Among these, PCIE4 and PCIE6 use different unit types, but share the same config register layout, and the generic PCIe PMON events apply to both. Additionally, ignore the broken MSE unit. Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251231224233.113839-5-zide.chen@intel.com
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Lines changed: 243 additions & 0 deletions

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‎arch/x86/events/intel/uncore.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1831,6 +1831,14 @@ static const struct uncore_plat_init gnr_uncore_init __initconst = {
18311831
.domain[0].units_ignore = gnr_uncore_units_ignore,
18321832
};
18331833

1834+
static const struct uncore_plat_init dmr_uncore_init __initconst = {
1835+
.pci_init = dmr_uncore_pci_init,
1836+
.mmio_init = dmr_uncore_mmio_init,
1837+
.domain[0].base_is_pci = true,
1838+
.domain[0].discovery_base = DMR_UNCORE_DISCOVERY_TABLE_DEVICE,
1839+
.domain[0].units_ignore = dmr_uncore_imh_units_ignore,
1840+
};
1841+
18341842
static const struct uncore_plat_init generic_uncore_init __initconst = {
18351843
.cpu_init = intel_uncore_generic_uncore_cpu_init,
18361844
.pci_init = intel_uncore_generic_uncore_pci_init,
@@ -1898,6 +1906,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
18981906
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_uncore_init),
18991907
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_uncore_init),
19001908
X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_uncore_init),
1909+
X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, &dmr_uncore_init),
19011910
{},
19021911
};
19031912
MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);

‎arch/x86/events/intel/uncore.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -614,6 +614,7 @@ extern struct pci_extra_dev *uncore_extra_pci_dev;
614614
extern struct event_constraint uncore_constraint_empty;
615615
extern int spr_uncore_units_ignore[];
616616
extern int gnr_uncore_units_ignore[];
617+
extern int dmr_uncore_imh_units_ignore[];
617618

618619
/* uncore_snb.c */
619620
int snb_uncore_pci_init(void);
@@ -662,6 +663,8 @@ void spr_uncore_mmio_init(void);
662663
int gnr_uncore_pci_init(void);
663664
void gnr_uncore_cpu_init(void);
664665
void gnr_uncore_mmio_init(void);
666+
int dmr_uncore_pci_init(void);
667+
void dmr_uncore_mmio_init(void);
665668

666669
/* uncore_nhmex.c */
667670
void nhmex_uncore_cpu_init(void);

‎arch/x86/events/intel/uncore_discovery.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55

66
/* Generic device ID of a discovery table device */
77
#define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
8+
/* Device ID used on DMR */
9+
#define DMR_UNCORE_DISCOVERY_TABLE_DEVICE 0x09a1
810
/* Capability ID for a discovery table device */
911
#define UNCORE_EXT_CAP_ID_DISCOVERY 0x23
1012
/* First DVSEC offset */

‎arch/x86/events/intel/uncore_snbep.c‎

Lines changed: 229 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -471,6 +471,14 @@
471471

472472
#define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
473473

474+
/* DMR */
475+
#define DMR_CXLCM_EVENT_MASK_EXT 0xf
476+
#define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
477+
#define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
478+
479+
#define DMR_IMC_PMON_FIXED_CTR 0x18
480+
#define DMR_IMC_PMON_FIXED_CTL 0x10
481+
474482
DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
475483
DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
476484
DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
@@ -486,6 +494,10 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
486494
DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
487495
DEFINE_UNCORE_FORMAT_ATTR(tid_en2, tid_en, "config:16");
488496
DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
497+
DEFINE_UNCORE_FORMAT_ATTR(inv2, inv, "config:21");
498+
DEFINE_UNCORE_FORMAT_ATTR(thresh_ext, thresh_ext, "config:32-35");
499+
DEFINE_UNCORE_FORMAT_ATTR(thresh10, thresh, "config:23-32");
500+
DEFINE_UNCORE_FORMAT_ATTR(thresh9_2, thresh, "config:23-31");
489501
DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35");
490502
DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
491503
DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29");
@@ -494,6 +506,13 @@ DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
494506
DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
495507
DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
496508
DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31");
509+
DEFINE_UNCORE_FORMAT_ATTR(port_en, port_en, "config:32-35");
510+
DEFINE_UNCORE_FORMAT_ATTR(rs3_sel, rs3_sel, "config:36");
511+
DEFINE_UNCORE_FORMAT_ATTR(rx_sel, rx_sel, "config:37");
512+
DEFINE_UNCORE_FORMAT_ATTR(tx_sel, tx_sel, "config:38");
513+
DEFINE_UNCORE_FORMAT_ATTR(iep_sel, iep_sel, "config:39");
514+
DEFINE_UNCORE_FORMAT_ATTR(vc_sel, vc_sel, "config:40-47");
515+
DEFINE_UNCORE_FORMAT_ATTR(port_sel, port_sel, "config:48-55");
497516
DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43");
498517
DEFINE_UNCORE_FORMAT_ATTR(ch_mask2, ch_mask, "config:36-47");
499518
DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46");
@@ -6709,3 +6728,213 @@ void gnr_uncore_mmio_init(void)
67096728
}
67106729

67116730
/* end of GNR uncore support */
6731+
6732+
/* DMR uncore support */
6733+
#define UNCORE_DMR_NUM_UNCORE_TYPES 52
6734+
6735+
static struct attribute *dmr_imc_uncore_formats_attr[] = {
6736+
&format_attr_event.attr,
6737+
&format_attr_umask.attr,
6738+
&format_attr_edge.attr,
6739+
&format_attr_inv.attr,
6740+
&format_attr_thresh10.attr,
6741+
NULL,
6742+
};
6743+
6744+
static const struct attribute_group dmr_imc_uncore_format_group = {
6745+
.name = "format",
6746+
.attrs = dmr_imc_uncore_formats_attr,
6747+
};
6748+
6749+
static struct intel_uncore_type dmr_uncore_imc = {
6750+
.name = "imc",
6751+
.fixed_ctr_bits = 48,
6752+
.fixed_ctr = DMR_IMC_PMON_FIXED_CTR,
6753+
.fixed_ctl = DMR_IMC_PMON_FIXED_CTL,
6754+
.ops = &spr_uncore_mmio_ops,
6755+
.format_group = &dmr_imc_uncore_format_group,
6756+
.attr_update = uncore_alias_groups,
6757+
};
6758+
6759+
static struct attribute *dmr_sca_uncore_formats_attr[] = {
6760+
&format_attr_event.attr,
6761+
&format_attr_umask_ext5.attr,
6762+
&format_attr_edge.attr,
6763+
&format_attr_inv.attr,
6764+
&format_attr_thresh8.attr,
6765+
NULL,
6766+
};
6767+
6768+
static const struct attribute_group dmr_sca_uncore_format_group = {
6769+
.name = "format",
6770+
.attrs = dmr_sca_uncore_formats_attr,
6771+
};
6772+
6773+
static struct intel_uncore_type dmr_uncore_sca = {
6774+
.name = "sca",
6775+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6776+
.format_group = &dmr_sca_uncore_format_group,
6777+
.attr_update = uncore_alias_groups,
6778+
};
6779+
6780+
static struct attribute *dmr_cxlcm_uncore_formats_attr[] = {
6781+
&format_attr_event.attr,
6782+
&format_attr_umask.attr,
6783+
&format_attr_edge.attr,
6784+
&format_attr_inv2.attr,
6785+
&format_attr_thresh9_2.attr,
6786+
&format_attr_port_en.attr,
6787+
NULL,
6788+
};
6789+
6790+
static const struct attribute_group dmr_cxlcm_uncore_format_group = {
6791+
.name = "format",
6792+
.attrs = dmr_cxlcm_uncore_formats_attr,
6793+
};
6794+
6795+
static struct intel_uncore_type dmr_uncore_cxlcm = {
6796+
.name = "cxlcm",
6797+
.event_mask = GENERIC_PMON_RAW_EVENT_MASK,
6798+
.event_mask_ext = DMR_CXLCM_EVENT_MASK_EXT,
6799+
.format_group = &dmr_cxlcm_uncore_format_group,
6800+
.attr_update = uncore_alias_groups,
6801+
};
6802+
6803+
static struct intel_uncore_type dmr_uncore_hamvf = {
6804+
.name = "hamvf",
6805+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6806+
.format_group = &dmr_sca_uncore_format_group,
6807+
.attr_update = uncore_alias_groups,
6808+
};
6809+
6810+
static struct intel_uncore_type dmr_uncore_ula = {
6811+
.name = "ula",
6812+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6813+
.format_group = &dmr_sca_uncore_format_group,
6814+
.attr_update = uncore_alias_groups,
6815+
};
6816+
6817+
static struct intel_uncore_type dmr_uncore_ubr = {
6818+
.name = "ubr",
6819+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6820+
.format_group = &dmr_sca_uncore_format_group,
6821+
.attr_update = uncore_alias_groups,
6822+
};
6823+
6824+
static struct attribute *dmr_pcie4_uncore_formats_attr[] = {
6825+
&format_attr_event.attr,
6826+
&format_attr_umask.attr,
6827+
&format_attr_edge.attr,
6828+
&format_attr_inv.attr,
6829+
&format_attr_thresh8.attr,
6830+
&format_attr_thresh_ext.attr,
6831+
&format_attr_rs3_sel.attr,
6832+
&format_attr_rx_sel.attr,
6833+
&format_attr_tx_sel.attr,
6834+
&format_attr_iep_sel.attr,
6835+
&format_attr_vc_sel.attr,
6836+
&format_attr_port_sel.attr,
6837+
NULL,
6838+
};
6839+
6840+
static const struct attribute_group dmr_pcie4_uncore_format_group = {
6841+
.name = "format",
6842+
.attrs = dmr_pcie4_uncore_formats_attr,
6843+
};
6844+
6845+
static struct intel_uncore_type dmr_uncore_pcie4 = {
6846+
.name = "pcie4",
6847+
.event_mask_ext = DMR_PCIE4_EVENT_MASK_EXT,
6848+
.format_group = &dmr_pcie4_uncore_format_group,
6849+
.attr_update = uncore_alias_groups,
6850+
};
6851+
6852+
static struct intel_uncore_type dmr_uncore_crs = {
6853+
.name = "crs",
6854+
.attr_update = uncore_alias_groups,
6855+
};
6856+
6857+
static struct intel_uncore_type dmr_uncore_cpc = {
6858+
.name = "cpc",
6859+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6860+
.format_group = &dmr_sca_uncore_format_group,
6861+
.attr_update = uncore_alias_groups,
6862+
};
6863+
6864+
static struct intel_uncore_type dmr_uncore_itc = {
6865+
.name = "itc",
6866+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6867+
.format_group = &dmr_sca_uncore_format_group,
6868+
.attr_update = uncore_alias_groups,
6869+
};
6870+
6871+
static struct intel_uncore_type dmr_uncore_otc = {
6872+
.name = "otc",
6873+
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6874+
.format_group = &dmr_sca_uncore_format_group,
6875+
.attr_update = uncore_alias_groups,
6876+
};
6877+
6878+
static struct intel_uncore_type dmr_uncore_cms = {
6879+
.name = "cms",
6880+
.attr_update = uncore_alias_groups,
6881+
};
6882+
6883+
static struct intel_uncore_type dmr_uncore_pcie6 = {
6884+
.name = "pcie6",
6885+
.event_mask_ext = DMR_PCIE4_EVENT_MASK_EXT,
6886+
.format_group = &dmr_pcie4_uncore_format_group,
6887+
.attr_update = uncore_alias_groups,
6888+
};
6889+
6890+
static struct intel_uncore_type *dmr_uncores[UNCORE_DMR_NUM_UNCORE_TYPES] = {
6891+
NULL, NULL, NULL, NULL,
6892+
&spr_uncore_pcu,
6893+
&gnr_uncore_ubox,
6894+
&dmr_uncore_imc,
6895+
NULL,
6896+
NULL, NULL, NULL, NULL,
6897+
NULL, NULL, NULL, NULL,
6898+
NULL, NULL, NULL, NULL,
6899+
NULL, NULL, NULL,
6900+
&dmr_uncore_sca,
6901+
&dmr_uncore_cxlcm,
6902+
NULL, NULL, NULL,
6903+
NULL, NULL,
6904+
&dmr_uncore_hamvf,
6905+
NULL,
6906+
NULL, NULL, NULL,
6907+
&dmr_uncore_ula,
6908+
NULL, NULL, NULL, NULL,
6909+
NULL, NULL, NULL,
6910+
&dmr_uncore_ubr,
6911+
NULL,
6912+
&dmr_uncore_pcie4,
6913+
&dmr_uncore_crs,
6914+
&dmr_uncore_cpc,
6915+
&dmr_uncore_itc,
6916+
&dmr_uncore_otc,
6917+
&dmr_uncore_cms,
6918+
&dmr_uncore_pcie6,
6919+
};
6920+
6921+
int dmr_uncore_imh_units_ignore[] = {
6922+
0x13, /* MSE */
6923+
UNCORE_IGNORE_END
6924+
};
6925+
6926+
int dmr_uncore_pci_init(void)
6927+
{
6928+
uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
6929+
UNCORE_DMR_NUM_UNCORE_TYPES,
6930+
dmr_uncores);
6931+
return 0;
6932+
}
6933+
void dmr_uncore_mmio_init(void)
6934+
{
6935+
uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL,
6936+
UNCORE_DMR_NUM_UNCORE_TYPES,
6937+
dmr_uncores);
6938+
}
6939+
6940+
/* end of DMR uncore support */

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