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thermal/drivers/mediatek/lvts_thermal: Add MT8196 support
Add LVTS driver support for MT8196. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Laura Nao <laura.nao@collabora.com> Link: https://patch.msgid.link/20251125-mt8196-lvts-v4-v5-7-6db7eb903fb7@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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‎drivers/thermal/mediatek/lvts_thermal.c‎

Lines changed: 165 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,10 @@
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#define LVTS_COEFF_B_MT8195 250460
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#define LVTS_COEFF_A_MT7988 -204650
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#define LVTS_COEFF_B_MT7988 204650
95+
#define LVTS_COEFF_A_MT8196 391460
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#define LVTS_COEFF_B_MT8196 -391460
97+
98+
#define LVTS_MSR_OFFSET_MT8196 -984
9599

96100
#define LVTS_MSR_READ_TIMEOUT_US 400
97101
#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
@@ -100,6 +104,7 @@
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101105
#define LVTS_MAX_CAL_OFFSETS 3
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#define LVTS_NUM_CAL_OFFSETS_MT7988 3
107+
#define LVTS_NUM_CAL_OFFSETS_MT8196 2
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104109
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
105110
static int golden_temp_offset;
@@ -784,6 +789,39 @@ static int lvts_decode_sensor_calibration(const struct lvts_sensor_data *sensor,
784789
* <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
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* 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
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*
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* MT8196 :
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* Stream index map for MCU Domain mt8196 :
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*
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* <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2-->
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* 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
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*
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* <-sensor#5--> <-sensor#4--> <-sensor#7--> <-sensor#6-->
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* 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
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*
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* <-sensor#9--> <-sensor#8--> <-sensor#11-> <-sensor#10->
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* 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0X1B
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*
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* <-sensor#13-> <-sensor#12-> <-sensor#15-> <-sensor#14->
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* 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
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*
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* Stream index map for APU Domain mt8196 :
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*
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* <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2-->
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* 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
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*
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* Stream index map for GPU Domain mt8196 :
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*
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* <-sensor#1--> <-sensor#0-->
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* 0x2C | 0x2D | 0x2E | 0x2F
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*
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* Stream index map for AP Domain mt8196 :
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*
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* <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2-->
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* 0x30 | 0x31 | 0x32 | 0x33 | 0x34 | 0x35 | 0x36 | 0x37
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*
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* <-sensor#5--> <-sensor#4--> <-sensor#6--> <-sensor#7-->
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* 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
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*
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* Note: In some cases, values don't strictly follow a little endian ordering.
788826
* The data description gives byte offsets constituting each calibration value
789827
* for each sensor.
@@ -1849,11 +1887,112 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
18491887
}
18501888
};
18511889

1890+
static const struct lvts_ctrl_data mt8196_lvts_mcu_data_ctrl[] = {
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{
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.lvts_sensor = {
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{ .dt_id = MT8196_MCU_MEDIUM_CPU6_0,
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.cal_offsets = { 0x06, 0x07 } },
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{ .dt_id = MT8196_MCU_MEDIUM_CPU6_1,
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.cal_offsets = { 0x04, 0x05 } },
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{ .dt_id = MT8196_MCU_DSU2,
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.cal_offsets = { 0x0A, 0x0B } },
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{ .dt_id = MT8196_MCU_DSU3,
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.cal_offsets = { 0x08, 0x09 } }
1901+
},
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VALID_SENSOR_MAP(1, 1, 1, 1),
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.offset = 0x0,
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.mode = LVTS_MSR_ATP_MODE,
1905+
},
1906+
{
1907+
.lvts_sensor = {
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{ .dt_id = MT8196_MCU_LITTLE_CPU3,
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.cal_offsets = { 0x0E, 0x0F } },
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{ .dt_id = MT8196_MCU_LITTLE_CPU0,
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.cal_offsets = { 0x0C, 0x0D } },
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{ .dt_id = MT8196_MCU_LITTLE_CPU1,
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.cal_offsets = { 0x12, 0x13 } },
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{ .dt_id = MT8196_MCU_LITTLE_CPU2,
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.cal_offsets = { 0x10, 0x11 } }
1916+
},
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VALID_SENSOR_MAP(1, 1, 1, 1),
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.offset = 0x100,
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.mode = LVTS_MSR_ATP_MODE,
1920+
},
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{
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.lvts_sensor = {
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{ .dt_id = MT8196_MCU_MEDIUM_CPU4_0,
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.cal_offsets = { 0x16, 0x17 } },
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{ .dt_id = MT8196_MCU_MEDIUM_CPU4_1,
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.cal_offsets = { 0x14, 0x15 } },
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{ .dt_id = MT8196_MCU_MEDIUM_CPU5_0,
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.cal_offsets = { 0x1A, 0x1B } },
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{ .dt_id = MT8196_MCU_MEDIUM_CPU5_1,
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.cal_offsets = { 0x18, 0x19 } }
1931+
},
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VALID_SENSOR_MAP(1, 1, 1, 1),
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.offset = 0x200,
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.mode = LVTS_MSR_ATP_MODE,
1935+
},
1936+
{
1937+
.lvts_sensor = {
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{ .dt_id = MT8196_MCU_DSU0,
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.cal_offsets = { 0x1E, 0x1F } },
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{ .dt_id = MT8196_MCU_DSU1,
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.cal_offsets = { 0x1C, 0x1D } },
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{ .dt_id = MT8196_MCU_BIG_CPU7_0,
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.cal_offsets = { 0x22, 0x23 } },
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{ .dt_id = MT8196_MCU_BIG_CPU7_1,
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.cal_offsets = { 0x20, 0x21 } }
1946+
},
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VALID_SENSOR_MAP(1, 1, 1, 1),
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.offset = 0x300,
1949+
.mode = LVTS_MSR_ATP_MODE,
1950+
}
1951+
};
1952+
1953+
static const struct lvts_ctrl_data mt8196_lvts_ap_data_ctrl[] = {
1954+
{
1955+
.lvts_sensor = {
1956+
{ .dt_id = MT8196_AP_TOP0,
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.cal_offsets = { 0x32, 0x33 } },
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{ .dt_id = MT8196_AP_TOP1,
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.cal_offsets = { 0x30, 0x31 } },
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{ .dt_id = MT8196_AP_TOP2,
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.cal_offsets = { 0x36, 0x37 } },
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{ .dt_id = MT8196_AP_TOP3,
1963+
.cal_offsets = { 0x34, 0x35 } }
1964+
},
1965+
VALID_SENSOR_MAP(1, 1, 1, 1),
1966+
.offset = 0x0,
1967+
.mode = LVTS_MSR_ATP_MODE,
1968+
},
1969+
{
1970+
.lvts_sensor = {
1971+
{ .dt_id = MT8196_AP_BOT0,
1972+
.cal_offsets = { 0x3A, 0x3B } },
1973+
{ .dt_id = MT8196_AP_BOT1,
1974+
.cal_offsets = { 0x38, 0x39 } },
1975+
{ .dt_id = MT8196_AP_BOT2,
1976+
.cal_offsets = { 0x3E, 0x3F } },
1977+
{ .dt_id = MT8196_AP_BOT3,
1978+
.cal_offsets = { 0x3C, 0x3D } }
1979+
},
1980+
VALID_SENSOR_MAP(1, 1, 1, 1),
1981+
.offset = 0x100,
1982+
.mode = LVTS_MSR_ATP_MODE,
1983+
}
1984+
};
1985+
18521986
static const struct lvts_platform_ops lvts_platform_ops_mt7988 = {
18531987
.lvts_raw_to_temp = lvts_raw_to_temp_mt7988,
18541988
.lvts_temp_to_raw = lvts_temp_to_raw_mt7988,
18551989
};
18561990

1991+
static const struct lvts_platform_ops lvts_platform_ops_mt8196 = {
1992+
.lvts_raw_to_temp = lvts_raw_to_temp_mt7988,
1993+
.lvts_temp_to_raw = lvts_temp_to_raw_mt8196,
1994+
};
1995+
18571996
static const struct lvts_data mt7988_lvts_ap_data = {
18581997
.lvts_ctrl = mt7988_lvts_ap_data_ctrl,
18591998
.conn_cmd = mt7988_conn_cmds,
@@ -1973,6 +2112,30 @@ static const struct lvts_data mt8195_lvts_ap_data = {
19732112
.ops = &lvts_platform_ops_mt7988,
19742113
};
19752114

2115+
static const struct lvts_data mt8196_lvts_mcu_data = {
2116+
.lvts_ctrl = mt8196_lvts_mcu_data_ctrl,
2117+
.num_lvts_ctrl = ARRAY_SIZE(mt8196_lvts_mcu_data_ctrl),
2118+
.temp_factor = LVTS_COEFF_A_MT8196,
2119+
.temp_offset = LVTS_COEFF_B_MT8196,
2120+
.gt_calib_bit_offset = 0,
2121+
.def_calibration = 14437,
2122+
.num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT8196,
2123+
.msr_offset = LVTS_MSR_OFFSET_MT8196,
2124+
.ops = &lvts_platform_ops_mt8196,
2125+
};
2126+
2127+
static const struct lvts_data mt8196_lvts_ap_data = {
2128+
.lvts_ctrl = mt8196_lvts_ap_data_ctrl,
2129+
.num_lvts_ctrl = ARRAY_SIZE(mt8196_lvts_ap_data_ctrl),
2130+
.temp_factor = LVTS_COEFF_A_MT8196,
2131+
.temp_offset = LVTS_COEFF_B_MT8196,
2132+
.gt_calib_bit_offset = 0,
2133+
.def_calibration = 14437,
2134+
.num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT8196,
2135+
.msr_offset = LVTS_MSR_OFFSET_MT8196,
2136+
.ops = &lvts_platform_ops_mt8196,
2137+
};
2138+
19762139
static const struct of_device_id lvts_of_match[] = {
19772140
{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
19782141
{ .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data },
@@ -1982,6 +2145,8 @@ static const struct of_device_id lvts_of_match[] = {
19822145
{ .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
19832146
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
19842147
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
2148+
{ .compatible = "mediatek,mt8196-lvts-mcu", .data = &mt8196_lvts_mcu_data },
2149+
{ .compatible = "mediatek,mt8196-lvts-ap", .data = &mt8196_lvts_ap_data },
19852150
{},
19862151
};
19872152
MODULE_DEVICE_TABLE(of, lvts_of_match);

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