@@ -17,23 +17,6 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
1717 return container_of (hw , struct mtk_clk_mux , hw );
1818}
1919
20- static int mtk_clk_mux_enable (struct clk_hw * hw )
21- {
22- struct mtk_clk_mux * mux = to_mtk_clk_mux (hw );
23- u32 mask = BIT (mux -> data -> gate_shift );
24-
25- return regmap_update_bits (mux -> regmap , mux -> data -> mux_ofs ,
26- mask , ~mask );
27- }
28-
29- static void mtk_clk_mux_disable (struct clk_hw * hw )
30- {
31- struct mtk_clk_mux * mux = to_mtk_clk_mux (hw );
32- u32 mask = BIT (mux -> data -> gate_shift );
33-
34- regmap_update_bits (mux -> regmap , mux -> data -> mux_ofs , mask , mask );
35- }
36-
3720static int mtk_clk_mux_enable_setclr (struct clk_hw * hw )
3821{
3922 struct mtk_clk_mux * mux = to_mtk_clk_mux (hw );
@@ -72,28 +55,6 @@ static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
7255 return val ;
7356}
7457
75- static int mtk_clk_mux_set_parent_lock (struct clk_hw * hw , u8 index )
76- {
77- struct mtk_clk_mux * mux = to_mtk_clk_mux (hw );
78- u32 mask = GENMASK (mux -> data -> mux_width - 1 , 0 );
79- unsigned long flags = 0 ;
80-
81- if (mux -> lock )
82- spin_lock_irqsave (mux -> lock , flags );
83- else
84- __acquire (mux -> lock );
85-
86- regmap_update_bits (mux -> regmap , mux -> data -> mux_ofs , mask ,
87- index << mux -> data -> mux_shift );
88-
89- if (mux -> lock )
90- spin_unlock_irqrestore (mux -> lock , flags );
91- else
92- __release (mux -> lock );
93-
94- return 0 ;
95- }
96-
9758static int mtk_clk_mux_set_parent_setclr_lock (struct clk_hw * hw , u8 index )
9859{
9960 struct mtk_clk_mux * mux = to_mtk_clk_mux (hw );
@@ -129,25 +90,7 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
12990 return 0 ;
13091}
13192
132- const struct clk_ops mtk_mux_ops = {
133- .get_parent = mtk_clk_mux_get_parent ,
134- .set_parent = mtk_clk_mux_set_parent_lock ,
135- };
136-
137- const struct clk_ops mtk_mux_clr_set_upd_ops = {
138- .get_parent = mtk_clk_mux_get_parent ,
139- .set_parent = mtk_clk_mux_set_parent_setclr_lock ,
140- };
141-
142- const struct clk_ops mtk_mux_gate_ops = {
143- .enable = mtk_clk_mux_enable ,
144- .disable = mtk_clk_mux_disable ,
145- .is_enabled = mtk_clk_mux_is_enabled ,
146- .get_parent = mtk_clk_mux_get_parent ,
147- .set_parent = mtk_clk_mux_set_parent_lock ,
148- };
149-
150- const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
93+ static const struct clk_ops mtk_mux_ops = {
15194 .enable = mtk_clk_mux_enable_setclr ,
15295 .disable = mtk_clk_mux_disable_setclr ,
15396 .is_enabled = mtk_clk_mux_is_enabled ,
@@ -171,7 +114,7 @@ static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
171114 init .flags = mux -> flags | CLK_SET_RATE_PARENT ;
172115 init .parent_names = mux -> parent_names ;
173116 init .num_parents = mux -> num_parents ;
174- init .ops = mux -> ops ;
117+ init .ops = & mtk_mux_ops ;
175118
176119 clk_mux -> regmap = regmap ;
177120 clk_mux -> data = mux ;
0 commit comments