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Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next
 - Make clk_ops::determine_rate mandatory for muxes * clk-renesas: clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() clk: renesas: mstp: Convert to readl_poll_timeout_atomic() clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic() iopoll: Do not use timekeeping in read_poll_timeout_atomic() iopoll: Call cpu_relax() in busy loops clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write clk: renesas: r8a779a0: Add PWM clock * clk-determine-rate: (71 commits) clk: sprd: composite: Simplify determine_rate implementation ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate() clk: Fix best_parent_rate after moving code into a separate function clk: Forbid to register a mux without determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate clk: tegra: super: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5341: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate ... * clk-allwinner: clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux * clk-samsung: clk: samsung: add CONFIG_OF dependency clk: samsung: Re-add support for Exynos4212 CPU clock clk: samsung: Add Exynos4212 compatible to CLKOUT driver dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible * clk-amlogic: MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK clk: meson: pll: remove unneeded semicolon clk: meson: a1: Staticize rtc clk clk: meson: a1: add Amlogic A1 Peripherals clock controller driver clk: meson: a1: add Amlogic A1 PLL clock controller driver clk: meson: introduce new pll power-on sequence for A1 SoC family clk: meson: make pll rst bit as optional dt-bindings: clock: meson: add A1 Peripherals clock controller bindings dt-bindings: clock: meson: add A1 PLL clock controller bindings
6 parents e155a36 + e90f15b + 587dd44 + 29d7088 + 59374d0 + 9390860 commit 6e11940

72 files changed

Lines changed: 3713 additions & 283 deletions

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‎Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Amlogic A1 Peripherals Clock Control Unit
8+
9+
maintainers:
10+
- Neil Armstrong <neil.armstrong@linaro.org>
11+
- Jerome Brunet <jbrunet@baylibre.com>
12+
- Jian Hu <jian.hu@jian.hu.com>
13+
- Dmitry Rokosov <ddrokosov@sberdevices.ru>
14+
15+
properties:
16+
compatible:
17+
const: amlogic,a1-peripherals-clkc
18+
19+
'#clock-cells':
20+
const: 1
21+
22+
reg:
23+
maxItems: 1
24+
25+
clocks:
26+
items:
27+
- description: input fixed pll div2
28+
- description: input fixed pll div3
29+
- description: input fixed pll div5
30+
- description: input fixed pll div7
31+
- description: input hifi pll
32+
- description: input oscillator (usually at 24MHz)
33+
34+
clock-names:
35+
items:
36+
- const: fclk_div2
37+
- const: fclk_div3
38+
- const: fclk_div5
39+
- const: fclk_div7
40+
- const: hifi_pll
41+
- const: xtal
42+
43+
required:
44+
- compatible
45+
- '#clock-cells'
46+
- reg
47+
- clocks
48+
- clock-names
49+
50+
additionalProperties: false
51+
52+
examples:
53+
- |
54+
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
55+
apb {
56+
#address-cells = <2>;
57+
#size-cells = <2>;
58+
59+
clock-controller@800 {
60+
compatible = "amlogic,a1-peripherals-clkc";
61+
reg = <0 0x800 0 0x104>;
62+
#clock-cells = <1>;
63+
clocks = <&clkc_pll CLKID_FCLK_DIV2>,
64+
<&clkc_pll CLKID_FCLK_DIV3>,
65+
<&clkc_pll CLKID_FCLK_DIV5>,
66+
<&clkc_pll CLKID_FCLK_DIV7>,
67+
<&clkc_pll CLKID_HIFI_PLL>,
68+
<&xtal>;
69+
clock-names = "fclk_div2", "fclk_div3",
70+
"fclk_div5", "fclk_div7",
71+
"hifi_pll", "xtal";
72+
};
73+
};

‎Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Amlogic A1 PLL Clock Control Unit
8+
9+
maintainers:
10+
- Neil Armstrong <neil.armstrong@linaro.org>
11+
- Jerome Brunet <jbrunet@baylibre.com>
12+
- Jian Hu <jian.hu@jian.hu.com>
13+
- Dmitry Rokosov <ddrokosov@sberdevices.ru>
14+
15+
properties:
16+
compatible:
17+
const: amlogic,a1-pll-clkc
18+
19+
'#clock-cells':
20+
const: 1
21+
22+
reg:
23+
maxItems: 1
24+
25+
clocks:
26+
items:
27+
- description: input fixpll_in
28+
- description: input hifipll_in
29+
30+
clock-names:
31+
items:
32+
- const: fixpll_in
33+
- const: hifipll_in
34+
35+
required:
36+
- compatible
37+
- '#clock-cells'
38+
- reg
39+
- clocks
40+
- clock-names
41+
42+
additionalProperties: false
43+
44+
examples:
45+
- |
46+
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
47+
apb {
48+
#address-cells = <2>;
49+
#size-cells = <2>;
50+
51+
clock-controller@7c80 {
52+
compatible = "amlogic,a1-pll-clkc";
53+
reg = <0 0x7c80 0 0x18c>;
54+
#clock-cells = <1>;
55+
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
56+
<&clkc_periphs CLKID_HIFIPLL_IN>;
57+
clock-names = "fixpll_in", "hifipll_in";
58+
};
59+
};

‎Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ properties:
2424
- samsung,exynos3250-cmu-dmc
2525
- samsung,exynos3250-cmu-isp
2626
- samsung,exynos4210-clock
27+
- samsung,exynos4212-clock
2728
- samsung,exynos4412-clock
2829
- samsung,exynos5250-clock
2930
- items:

‎MAINTAINERS‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1888,6 +1888,7 @@ L: linux-amlogic@lists.infradead.org
18881888
S: Maintained
18891889
F: Documentation/devicetree/bindings/clock/amlogic*
18901890
F: drivers/clk/meson/
1891+
F: include/dt-bindings/clock/amlogic,a1*
18911892
F: include/dt-bindings/clock/gxbb*
18921893
F: include/dt-bindings/clock/meson*
18931894

‎drivers/clk/actions/owl-composite.c‎

Lines changed: 24 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -53,13 +53,19 @@ static int owl_comp_is_enabled(struct clk_hw *hw)
5353
return owl_gate_clk_is_enabled(common, &comp->gate_hw);
5454
}
5555

56-
static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,
57-
unsigned long *parent_rate)
56+
static int owl_comp_div_determine_rate(struct clk_hw *hw,
57+
struct clk_rate_request *req)
5858
{
5959
struct owl_composite *comp = hw_to_owl_comp(hw);
60+
long rate;
6061

61-
return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
62-
rate, parent_rate);
62+
rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
63+
req->rate, &req->best_parent_rate);
64+
if (rate < 0)
65+
return rate;
66+
67+
req->rate = rate;
68+
return 0;
6369
}
6470

6571
static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
@@ -80,14 +86,20 @@ static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
8086
rate, parent_rate);
8187
}
8288

83-
static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,
84-
unsigned long *parent_rate)
89+
static int owl_comp_fact_determine_rate(struct clk_hw *hw,
90+
struct clk_rate_request *req)
8591
{
8692
struct owl_composite *comp = hw_to_owl_comp(hw);
93+
long rate;
8794

88-
return owl_factor_helper_round_rate(&comp->common,
89-
&comp->rate.factor_hw,
90-
rate, parent_rate);
95+
rate = owl_factor_helper_round_rate(&comp->common,
96+
&comp->rate.factor_hw,
97+
req->rate, &req->best_parent_rate);
98+
if (rate < 0)
99+
return rate;
100+
101+
req->rate = rate;
102+
return 0;
91103
}
92104

93105
static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,
@@ -152,7 +164,7 @@ const struct clk_ops owl_comp_div_ops = {
152164
.is_enabled = owl_comp_is_enabled,
153165

154166
/* div_ops */
155-
.round_rate = owl_comp_div_round_rate,
167+
.determine_rate = owl_comp_div_determine_rate,
156168
.recalc_rate = owl_comp_div_recalc_rate,
157169
.set_rate = owl_comp_div_set_rate,
158170
};
@@ -169,7 +181,7 @@ const struct clk_ops owl_comp_fact_ops = {
169181
.is_enabled = owl_comp_is_enabled,
170182

171183
/* fact_ops */
172-
.round_rate = owl_comp_fact_round_rate,
184+
.determine_rate = owl_comp_fact_determine_rate,
173185
.recalc_rate = owl_comp_fact_recalc_rate,
174186
.set_rate = owl_comp_fact_set_rate,
175187
};
@@ -189,6 +201,7 @@ const struct clk_ops owl_comp_fix_fact_ops = {
189201

190202
const struct clk_ops owl_comp_pass_ops = {
191203
/* mux_ops */
204+
.determine_rate = clk_hw_determine_rate_no_reparent,
192205
.get_parent = owl_comp_get_parent,
193206
.set_parent = owl_comp_set_parent,
194207

‎drivers/clk/at91/clk-main.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -533,6 +533,7 @@ static const struct clk_ops sam9x5_main_ops = {
533533
.prepare = clk_sam9x5_main_prepare,
534534
.is_prepared = clk_sam9x5_main_is_prepared,
535535
.recalc_rate = clk_sam9x5_main_recalc_rate,
536+
.determine_rate = clk_hw_determine_rate_no_reparent,
536537
.set_parent = clk_sam9x5_main_set_parent,
537538
.get_parent = clk_sam9x5_main_get_parent,
538539
.save_context = clk_sam9x5_main_save_context,

‎drivers/clk/at91/clk-smd.c‎

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -36,26 +36,31 @@ static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
3636
return parent_rate / (smddiv + 1);
3737
}
3838

39-
static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
40-
unsigned long *parent_rate)
39+
static int at91sam9x5_clk_smd_determine_rate(struct clk_hw *hw,
40+
struct clk_rate_request *req)
4141
{
4242
unsigned long div;
4343
unsigned long bestrate;
4444
unsigned long tmp;
4545

46-
if (rate >= *parent_rate)
47-
return *parent_rate;
46+
if (req->rate >= req->best_parent_rate) {
47+
req->rate = req->best_parent_rate;
48+
return 0;
49+
}
4850

49-
div = *parent_rate / rate;
50-
if (div > SMD_MAX_DIV)
51-
return *parent_rate / (SMD_MAX_DIV + 1);
51+
div = req->best_parent_rate / req->rate;
52+
if (div > SMD_MAX_DIV) {
53+
req->rate = req->best_parent_rate / (SMD_MAX_DIV + 1);
54+
return 0;
55+
}
5256

53-
bestrate = *parent_rate / div;
54-
tmp = *parent_rate / (div + 1);
55-
if (bestrate - rate > rate - tmp)
57+
bestrate = req->best_parent_rate / div;
58+
tmp = req->best_parent_rate / (div + 1);
59+
if (bestrate - req->rate > req->rate - tmp)
5660
bestrate = tmp;
5761

58-
return bestrate;
62+
req->rate = bestrate;
63+
return 0;
5964
}
6065

6166
static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
@@ -98,7 +103,7 @@ static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
98103

99104
static const struct clk_ops at91sam9x5_smd_ops = {
100105
.recalc_rate = at91sam9x5_clk_smd_recalc_rate,
101-
.round_rate = at91sam9x5_clk_smd_round_rate,
106+
.determine_rate = at91sam9x5_clk_smd_determine_rate,
102107
.get_parent = at91sam9x5_clk_smd_get_parent,
103108
.set_parent = at91sam9x5_clk_smd_set_parent,
104109
.set_rate = at91sam9x5_clk_smd_set_rate,

‎drivers/clk/at91/sckc.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,7 @@ static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
310310
}
311311

312312
static const struct clk_ops sam9x5_slow_ops = {
313+
.determine_rate = clk_hw_determine_rate_no_reparent,
313314
.set_parent = clk_sam9x5_slow_set_parent,
314315
.get_parent = clk_sam9x5_slow_get_parent,
315316
};

‎drivers/clk/berlin/berlin2-div.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,7 @@ static unsigned long berlin2_div_recalc_rate(struct clk_hw *hw,
210210
}
211211

212212
static const struct clk_ops berlin2_div_rate_ops = {
213+
.determine_rate = clk_hw_determine_rate_no_reparent,
213214
.recalc_rate = berlin2_div_recalc_rate,
214215
};
215216

‎drivers/clk/clk-axi-clkgen.c‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -384,23 +384,25 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
384384
return 0;
385385
}
386386

387-
static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
388-
unsigned long *parent_rate)
387+
static int axi_clkgen_determine_rate(struct clk_hw *hw,
388+
struct clk_rate_request *req)
389389
{
390390
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
391391
const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
392392
unsigned int d, m, dout;
393393
unsigned long long tmp;
394394

395-
axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);
395+
axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,
396+
&d, &m, &dout);
396397

397398
if (d == 0 || dout == 0 || m == 0)
398399
return -EINVAL;
399400

400-
tmp = (unsigned long long)*parent_rate * m;
401+
tmp = (unsigned long long)req->best_parent_rate * m;
401402
tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
402403

403-
return min_t(unsigned long long, tmp, LONG_MAX);
404+
req->rate = min_t(unsigned long long, tmp, LONG_MAX);
405+
return 0;
404406
}
405407

406408
static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
@@ -495,7 +497,7 @@ static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
495497

496498
static const struct clk_ops axi_clkgen_ops = {
497499
.recalc_rate = axi_clkgen_recalc_rate,
498-
.round_rate = axi_clkgen_round_rate,
500+
.determine_rate = axi_clkgen_determine_rate,
499501
.set_rate = axi_clkgen_set_rate,
500502
.enable = axi_clkgen_enable,
501503
.disable = axi_clkgen_disable,

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