|
84 | 84 | clock-frequency = <100000000>; |
85 | 85 | }; |
86 | 86 |
|
| 87 | + reg_1v5: regulator-1v5 { |
| 88 | + compatible = "regulator-fixed"; |
| 89 | + regulator-name = "1v5"; |
| 90 | + regulator-min-microvolt = <1500000>; |
| 91 | + regulator-max-microvolt = <1500000>; |
| 92 | + }; |
| 93 | + |
| 94 | + reg_1v8: regulator-1v8 { |
| 95 | + compatible = "regulator-fixed"; |
| 96 | + regulator-name = "1v8"; |
| 97 | + regulator-min-microvolt = <1800000>; |
| 98 | + regulator-max-microvolt = <1800000>; |
| 99 | + }; |
| 100 | + |
| 101 | + reg_2v8: regulator-1v8 { |
| 102 | + compatible = "regulator-fixed"; |
| 103 | + regulator-name = "2v8"; |
| 104 | + regulator-min-microvolt = <2800000>; |
| 105 | + regulator-max-microvolt = <2800000>; |
| 106 | + }; |
| 107 | + |
87 | 108 | reg_audio_3v3: regulator-audio-3v3 { |
88 | 109 | compatible = "regulator-fixed"; |
89 | 110 | regulator-name = "audio-3v3"; |
|
548 | 569 | pinctrl-0 = <&pinctrl_i2c2>; |
549 | 570 | status = "okay"; |
550 | 571 |
|
| 572 | + camera@3c { |
| 573 | + compatible = "ovti,ov5640"; |
| 574 | + reg = <0x3c>; |
| 575 | + pinctrl-names = "default"; |
| 576 | + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; |
| 577 | + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; |
| 578 | + clock-names = "xclk"; |
| 579 | + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; |
| 580 | + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; |
| 581 | + assigned-clock-rates = <24000000>; |
| 582 | + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; |
| 583 | + AVDD-supply = <®_2v8>; |
| 584 | + DVDD-supply = <®_1v5>; |
| 585 | + DOVDD-supply = <®_1v8>; |
| 586 | + status = "okay"; |
| 587 | + |
| 588 | + port { |
| 589 | + ov5640_mipi_0_ep: endpoint { |
| 590 | + remote-endpoint = <&mipi_csi0_ep>; |
| 591 | + data-lanes = <1 2>; |
| 592 | + }; |
| 593 | + }; |
| 594 | + }; |
| 595 | + |
551 | 596 | hdmi@3d { |
552 | 597 | compatible = "adi,adv7535"; |
553 | 598 | reg = <0x3d>; |
|
652 | 697 | */ |
653 | 698 | }; |
654 | 699 |
|
| 700 | +&isi_0 { |
| 701 | + status = "okay"; |
| 702 | +}; |
| 703 | + |
655 | 704 | &lcdif1 { |
656 | 705 | status = "okay"; |
657 | 706 | }; |
|
670 | 719 | status = "okay"; |
671 | 720 | }; |
672 | 721 |
|
| 722 | +&mipi_csi_0 { |
| 723 | + status = "okay"; |
| 724 | + |
| 725 | + ports { |
| 726 | + port@0 { |
| 727 | + mipi_csi0_ep: endpoint { |
| 728 | + remote-endpoint = <&ov5640_mipi_0_ep>; |
| 729 | + data-lanes = <1 2>; |
| 730 | + }; |
| 731 | + }; |
| 732 | + }; |
| 733 | +}; |
| 734 | + |
673 | 735 | &mipi_dsi { |
674 | 736 | samsung,esc-clock-frequency = <10000000>; |
675 | 737 | status = "okay"; |
|
843 | 905 | >; |
844 | 906 | }; |
845 | 907 |
|
| 908 | + pinctrl_csi_mclk: csi_mclk_grp { |
| 909 | + fsl,pins = < |
| 910 | + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50 |
| 911 | + >; |
| 912 | + }; |
| 913 | + |
| 914 | + pinctrl_csi0_pwn: csi0_pwn_grp { |
| 915 | + fsl,pins = < |
| 916 | + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 |
| 917 | + >; |
| 918 | + }; |
| 919 | + |
| 920 | + pinctrl_csi0_rst: csi0_rst_grp { |
| 921 | + fsl,pins = < |
| 922 | + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10 |
| 923 | + >; |
| 924 | + }; |
| 925 | + |
846 | 926 | pinctrl_eqos: eqosgrp { |
847 | 927 | fsl,pins = < |
848 | 928 | MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 |
|
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