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Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next
 - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Reimplement Loongson-1 clk driver with DT support - Clk driver support for Loongson-2 SoCs - Migrate socfpga clk driver to of_clk_add_hw_provider() * clk-mediatek: (84 commits) clk: mediatek: fhctl: Mark local variables static clk: mediatek: Use right match table, include mod_devicetable clk: mediatek: Add MT8188 adsp clock support clk: mediatek: Add MT8188 imp i2c wrapper clock support clk: mediatek: Add MT8188 wpesys clock support clk: mediatek: Add MT8188 vppsys1 clock support clk: mediatek: Add MT8188 vppsys0 clock support clk: mediatek: Add MT8188 vencsys clock support clk: mediatek: Add MT8188 vdosys1 clock support clk: mediatek: Add MT8188 vdosys0 clock support clk: mediatek: Add MT8188 vdecsys clock support clk: mediatek: Add MT8188 mfgcfg clock support clk: mediatek: Add MT8188 ipesys clock support clk: mediatek: Add MT8188 imgsys clock support clk: mediatek: Add MT8188 ccusys clock support clk: mediatek: Add MT8188 camsys clock support clk: mediatek: Add MT8188 infrastructure clock support clk: mediatek: Add MT8188 peripheral clock support clk: mediatek: Add MT8188 topckgen clock support clk: mediatek: Add MT8188 apmixedsys clock support ... * clk-sunplus: clk: Add Sunplus SP7021 clock driver * clk-loongson: clk: clk-loongson2: add clock controller driver support dt-bindings: clock: add loongson-2 boot clock index MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE MIPS: loongson32: Update the clock initialization clk: loongson1: Re-implement the clock driver clk: loongson1: Remove the outdated driver dt-bindings: clock: Add Loongson-1 clock * clk-socfpga: clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling
5 parents 4ec6a2f + cb9eee5 + d54c1fd + acc0ccf + 3dc6faa commit 6f7478e

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Lines changed: 9286 additions & 4897 deletions

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‎Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Loongson-1 Clock Controller
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maintainers:
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- Keguang Zhang <keguang.zhang@gmail.com>
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properties:
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compatible:
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enum:
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- loongson,ls1b-clk
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- loongson,ls1c-clk
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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clkc: clock-controller@1fe78030 {
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compatible = "loongson,ls1b-clk";
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reg = <0x1fe78030 0x8>;
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clocks = <&xtal>;
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#clock-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml‎

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@@ -16,7 +16,12 @@ description: |
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properties:
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compatible:
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const: mediatek,mt8186-fhctl
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enum:
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- mediatek,mt6795-fhctl
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- mediatek,mt8173-fhctl
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- mediatek,mt8186-fhctl
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- mediatek,mt8192-fhctl
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- mediatek,mt8195-fhctl
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reg:
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maxItems: 1

‎Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT8188
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maintainers:
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- Garmin Chang <garmin.chang@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices provide clock gate control in different IP blocks.
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properties:
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compatible:
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enum:
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- mediatek,mt8188-adsp-audio26m
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- mediatek,mt8188-camsys
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- mediatek,mt8188-camsys-rawa
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- mediatek,mt8188-camsys-rawb
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- mediatek,mt8188-camsys-yuva
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- mediatek,mt8188-camsys-yuvb
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- mediatek,mt8188-ccusys
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- mediatek,mt8188-imgsys
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- mediatek,mt8188-imgsys-wpe1
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- mediatek,mt8188-imgsys-wpe2
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- mediatek,mt8188-imgsys-wpe3
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- mediatek,mt8188-imgsys1-dip-nr
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- mediatek,mt8188-imgsys1-dip-top
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- mediatek,mt8188-imp-iic-wrap-c
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- mediatek,mt8188-imp-iic-wrap-en
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- mediatek,mt8188-imp-iic-wrap-w
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- mediatek,mt8188-ipesys
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- mediatek,mt8188-mfgcfg
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- mediatek,mt8188-vdecsys
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- mediatek,mt8188-vdecsys-soc
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- mediatek,mt8188-vencsys
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- mediatek,mt8188-vppsys0
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- mediatek,mt8188-vppsys1
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- mediatek,mt8188-wpesys
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- mediatek,mt8188-wpesys-vpp0
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@11283000 {
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compatible = "mediatek,mt8188-imp-iic-wrap-c";
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reg = <0x11283000 0x1000>;
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#clock-cells = <1>;
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};
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‎Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek System Clock Controller for MT8188
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maintainers:
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- Garmin Chang <garmin.chang@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The apmixedsys provides most of PLLs which generated from SoC 26m.
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The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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The mcusys provides mux control to select the clock source in AP MCU.
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The device nodes also provide the system control capacity for configuration.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8188-apmixedsys
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- mediatek,mt8188-infracfg-ao
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- mediatek,mt8188-pericfg-ao
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- mediatek,mt8188-topckgen
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@10000000 {
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compatible = "mediatek,mt8188-topckgen", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};

‎MAINTAINERS‎

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@@ -2849,6 +2849,7 @@ F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml
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F: arch/arm/boot/dts/sunplus-sp7021*.dts*
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F: arch/arm/configs/sp7021_*defconfig
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F: arch/arm/mach-sunplus/
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F: drivers/clk/clk-sp7021.c
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F: drivers/irqchip/irq-sp7021-intc.c
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F: drivers/reset/reset-sunplus.c
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F: include/dt-bindings/clock/sunplus,sp7021-clkc.h
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L: linux-clk@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
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F: drivers/clk/clk-loongson2.c
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F: include/dt-bindings/clock/loongson,ls2k-clk.h
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LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
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S: Maintained
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F: arch/mips/include/asm/mach-loongson32/
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F: arch/mips/loongson32/
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F: drivers/*/*/*loongson1*
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F: drivers/*/*loongson1*
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MIPS/LOONGSON2EF ARCHITECTURE

‎arch/mips/include/asm/mach-loongson32/platform.h‎

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extern struct platform_device ls1x_rtc_pdev;
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extern struct platform_device ls1x_wdt_pdev;
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void __init ls1x_clk_init(void);
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void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
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void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
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‎arch/mips/loongson32/common/time.c‎

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*/
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#include <linux/clk.h>
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#include <linux/of_clk.h>
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#include <linux/interrupt.h>
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#include <linux/sizes.h>
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#include <asm/time.h>
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struct clk *clk = NULL;
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/* initialize LS1X clocks */
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ls1x_clk_init();
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of_clk_init(NULL);
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#ifdef CONFIG_CEVT_CSRC_LS1X
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/* setup LS1X PWM timer */

‎drivers/clk/Kconfig‎

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This driver supports the clocking features of the Cirrus Logic
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Lochnagar audio development board.
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config COMMON_CLK_LOONGSON2
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bool "Clock driver for Loongson-2 SoC"
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depends on LOONGARCH || COMPILE_TEST
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help
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This driver provides support for clock controller on Loongson-2 SoC.
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The clock controller can generates and supplies clock to various
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peripherals within the SoC.
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Say Y here to support Loongson-2 SoC clock driver.
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config COMMON_CLK_NXP
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def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
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select REGMAP_MMIO if ARCH_LPC32XX
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help
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Support for the Canaan Kendryte K210 RISC-V SoC clocks.
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457+
config COMMON_CLK_SP7021
458+
tristate "Clock driver for Sunplus SP7021 SoC"
459+
depends on SOC_SP7021 || COMPILE_TEST
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default SOC_SP7021
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help
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This driver supports the Sunplus SP7021 SoC clocks.
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It implements SP7021 PLLs/gate.
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Not all features of the PLL are currently supported
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by the driver.
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source "drivers/clk/actions/Kconfig"
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source "drivers/clk/analogbits/Kconfig"
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source "drivers/clk/baikal-t1/Kconfig"

‎drivers/clk/Makefile‎

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@@ -43,6 +43,8 @@ obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
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obj-$(CONFIG_LMK04832) += clk-lmk04832.o
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obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
4545
obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
46+
obj-$(CONFIG_MACH_LOONGSON32) += clk-loongson1.o
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obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
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obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
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obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
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obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o
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obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
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obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o
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obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
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obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
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obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
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obj-y += ingenic/
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obj-$(CONFIG_ARCH_K3) += keystone/
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obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
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obj-$(CONFIG_MACH_LOONGSON32) += loongson1/
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obj-y += mediatek/
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obj-$(CONFIG_ARCH_MESON) += meson/
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obj-y += microchip/

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