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andy-shevgregkh
andy-shev
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gregkh
committed
serial: 8250_exar: Kill unneeded ->board_init()
We may reuse ->setup() for the same purpose as it was done before. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Parker Newman <pnewman@connecttech.com> Link: https://lore.kernel.org/r/20240503171917.2921250-8-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent c5f5974 commit 709bb04

1 file changed

Lines changed: 81 additions & 90 deletions

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‎drivers/tty/serial/8250/8250_exar.c‎

Lines changed: 81 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -237,14 +237,12 @@ struct exar8250_platform {
237237
* struct exar8250_board - board information
238238
* @num_ports: number of serial ports
239239
* @reg_shift: describes UART register mapping in PCI memory
240-
* @board_init: quirk run once at ->probe() stage before setting up ports
241240
* @setup: quirk run at ->probe() stage for each port
242241
* @exit: quirk run at ->remove() stage
243242
*/
244243
struct exar8250_board {
245244
unsigned int num_ports;
246245
unsigned int reg_shift;
247-
int (*board_init)(struct exar8250 *priv, struct pci_dev *pcidev);
248246
int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev,
249247
struct uart_8250_port *port, int idx);
250248
void (*exit)(struct pci_dev *pcidev);
@@ -907,9 +905,6 @@ static int cti_port_setup_common(struct exar8250 *priv,
907905
{
908906
int ret;
909907

910-
if (priv->osc_freq == 0)
911-
return -EINVAL;
912-
913908
port->port.port_id = idx;
914909
port->port.uartclk = priv->osc_freq;
915910

@@ -927,13 +922,44 @@ static int cti_port_setup_common(struct exar8250 *priv,
927922
return 0;
928923
}
929924

925+
static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
926+
{
927+
int ret;
928+
u16 cfg_val;
929+
930+
// FPGA OSC is fixed to the 33MHz PCI clock
931+
priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
932+
933+
// Enable external interrupts in special cfg space register
934+
ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val);
935+
if (ret)
936+
return pcibios_err_to_errno(ret);
937+
938+
cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
939+
ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val);
940+
if (ret)
941+
return pcibios_err_to_errno(ret);
942+
943+
// RS485 gate needs to be enabled; otherwise RTS/CTS will not work
944+
exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01);
945+
946+
return 0;
947+
}
948+
930949
static int cti_port_setup_fpga(struct exar8250 *priv,
931950
struct pci_dev *pcidev,
932951
struct uart_8250_port *port,
933952
int idx)
934953
{
935954
enum cti_port_type port_type;
936955
unsigned int offset;
956+
int ret;
957+
958+
if (idx == 0) {
959+
ret = cti_board_init_fpga(priv, pcidev);
960+
if (ret)
961+
return ret;
962+
}
937963

938964
port_type = cti_get_port_type_fpga(priv, pcidev, idx);
939965

@@ -953,6 +979,12 @@ static int cti_port_setup_fpga(struct exar8250 *priv,
953979
return cti_port_setup_common(priv, pcidev, idx, offset, port);
954980
}
955981

982+
static void cti_board_init_xr17v35x(struct exar8250 *priv, struct pci_dev *pcidev)
983+
{
984+
// XR17V35X uses the PCIe clock rather than an oscillator
985+
priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
986+
}
987+
956988
static int cti_port_setup_xr17v35x(struct exar8250 *priv,
957989
struct pci_dev *pcidev,
958990
struct uart_8250_port *port,
@@ -962,6 +994,9 @@ static int cti_port_setup_xr17v35x(struct exar8250 *priv,
962994
unsigned int offset;
963995
int ret;
964996

997+
if (idx == 0)
998+
cti_board_init_xr17v35x(priv, pcidev);
999+
9651000
port_type = cti_get_port_type_xr17v35x(priv, pcidev, idx);
9661001

9671002
offset = idx * UART_EXAR_XR17V35X_PORT_OFFSET;
@@ -999,6 +1034,22 @@ static int cti_port_setup_xr17v35x(struct exar8250 *priv,
9991034
return 0;
10001035
}
10011036

1037+
static void cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
1038+
{
1039+
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
1040+
1041+
/* enable interrupts on cards that need the "PLX fix" */
1042+
switch (pcidev->subsystem_device) {
1043+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
1044+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
1045+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
1046+
cti_plx_int_enable(priv);
1047+
break;
1048+
default:
1049+
break;
1050+
}
1051+
}
1052+
10021053
static int cti_port_setup_xr17v25x(struct exar8250 *priv,
10031054
struct pci_dev *pcidev,
10041055
struct uart_8250_port *port,
@@ -1008,6 +1059,9 @@ static int cti_port_setup_xr17v25x(struct exar8250 *priv,
10081059
unsigned int offset;
10091060
int ret;
10101061

1062+
if (idx == 0)
1063+
cti_board_init_xr17v25x(priv, pcidev);
1064+
10111065
port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
10121066

10131067
offset = idx * UART_EXAR_XR17V25X_PORT_OFFSET;
@@ -1055,6 +1109,25 @@ static int cti_port_setup_xr17v25x(struct exar8250 *priv,
10551109
return 0;
10561110
}
10571111

1112+
static void cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1113+
{
1114+
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1115+
1116+
/* enable interrupts on cards that need the "PLX fix" */
1117+
switch (pcidev->subsystem_device) {
1118+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1119+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1120+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1121+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1122+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1123+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1124+
cti_plx_int_enable(priv);
1125+
break;
1126+
default:
1127+
break;
1128+
}
1129+
}
1130+
10581131
static int cti_port_setup_xr17c15x(struct exar8250 *priv,
10591132
struct pci_dev *pcidev,
10601133
struct uart_8250_port *port,
@@ -1063,6 +1136,9 @@ static int cti_port_setup_xr17c15x(struct exar8250 *priv,
10631136
enum cti_port_type port_type;
10641137
unsigned int offset;
10651138

1139+
if (idx == 0)
1140+
cti_board_init_xr17c15x(priv, pcidev);
1141+
10661142
port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
10671143

10681144
offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
@@ -1096,78 +1172,6 @@ static int cti_port_setup_xr17c15x(struct exar8250 *priv,
10961172
return cti_port_setup_common(priv, pcidev, idx, offset, port);
10971173
}
10981174

1099-
static int cti_board_init_xr17v35x(struct exar8250 *priv,
1100-
struct pci_dev *pcidev)
1101-
{
1102-
// XR17V35X uses the PCIe clock rather than an oscillator
1103-
priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
1104-
1105-
return 0;
1106-
}
1107-
1108-
static int cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
1109-
{
1110-
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
1111-
1112-
/* enable interrupts on cards that need the "PLX fix" */
1113-
switch (pcidev->subsystem_device) {
1114-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
1115-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
1116-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
1117-
cti_plx_int_enable(priv);
1118-
break;
1119-
default:
1120-
break;
1121-
}
1122-
1123-
return 0;
1124-
}
1125-
1126-
static int cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1127-
{
1128-
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1129-
1130-
/* enable interrupts on cards that need the "PLX fix" */
1131-
switch (pcidev->subsystem_device) {
1132-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1133-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1134-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1135-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1136-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1137-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1138-
cti_plx_int_enable(priv);
1139-
break;
1140-
default:
1141-
break;
1142-
}
1143-
1144-
return 0;
1145-
}
1146-
1147-
static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
1148-
{
1149-
int ret;
1150-
u16 cfg_val;
1151-
1152-
// FPGA OSC is fixed to the 33MHz PCI clock
1153-
priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
1154-
1155-
// Enable external interrupts in special cfg space register
1156-
ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val);
1157-
if (ret)
1158-
return pcibios_err_to_errno(ret);
1159-
1160-
cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
1161-
ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val);
1162-
if (ret)
1163-
return pcibios_err_to_errno(ret);
1164-
1165-
// RS485 gate needs to be enabled; otherwise RTS/CTS will not work
1166-
exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01);
1167-
1168-
return 0;
1169-
}
1170-
11711175
static int
11721176
pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
11731177
struct uart_8250_port *port, int idx)
@@ -1574,15 +1578,6 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
15741578
if (rc)
15751579
return rc;
15761580

1577-
if (board->board_init) {
1578-
rc = board->board_init(priv, pcidev);
1579-
if (rc) {
1580-
dev_err_probe(&pcidev->dev, rc,
1581-
"failed to init serial board\n");
1582-
return rc;
1583-
}
1584-
}
1585-
15861581
for (i = 0; i < nr_ports && i < maxnr; i++) {
15871582
rc = board->setup(priv, pcidev, &uart, i);
15881583
if (rc) {
@@ -1664,22 +1659,18 @@ static const struct exar8250_board pbn_fastcom335_8 = {
16641659
};
16651660

16661661
static const struct exar8250_board pbn_cti_xr17c15x = {
1667-
.board_init = cti_board_init_xr17c15x,
16681662
.setup = cti_port_setup_xr17c15x,
16691663
};
16701664

16711665
static const struct exar8250_board pbn_cti_xr17v25x = {
1672-
.board_init = cti_board_init_xr17v25x,
16731666
.setup = cti_port_setup_xr17v25x,
16741667
};
16751668

16761669
static const struct exar8250_board pbn_cti_xr17v35x = {
1677-
.board_init = cti_board_init_xr17v35x,
16781670
.setup = cti_port_setup_xr17v35x,
16791671
};
16801672

16811673
static const struct exar8250_board pbn_cti_fpga = {
1682-
.board_init = cti_board_init_fpga,
16831674
.setup = cti_port_setup_fpga,
16841675
};
16851676

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