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Merge tag 'imx-dt64-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree for 6.5: - New board support: i.MX8MM based Emtop SoM & Baseboard, NXP i.MX8MM EVKB board, i.MX8MP based Gateworks Venice gw7905-2x device. - A series from Adam Ford to add Camera and Audio support for i.MX8M based Beacon boards. - Add Audio output support for i.MX8MP TQMa8MPxL/MBa8MPxL board. - Add HDMI and display support for imx8mm-evk and imx8mm-phg board. - Add coresight trace devices support for i.MX8MP SoC. - A couple of changes from Krzysztof Kozlowski to add missing cache properties. - A couple of changes from Laurent Pinchart to add CSIS and ISI devices for i.MX8MP SoC. - A series from Marek Vasut to add more devices for i.MX8MP, and enable SAI audio on i.MX8MP DHCOM PDK2 and PDK3. - Correct GSC vdd_bat data size for Gateworks Venice devices. - Add more device support for i.MX93, Watchdog, OCOTP, idle states, DDR performance monitor, etc. - Small and random clean-ups and device node additions. * tag 'imx-dt64-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (47 commits) arm64: dts: imx8mq: Pass address-cells/size-cells to mipi_dsi arm64: dts: imx8mq: Use 'dsi' as node name arm64: dts: imx8mp-venice-gw702x: fix GSC vdd_bat data size arm64: dts: imx8mq-tqma8mq-mba8mx: Remove invalid properties arm64: dts: imx8mq: Add missing pci property arm64: dts: imx8mq: Fix lcdif clocks arm64: dts: imx8mq: Fix lcdif compatible arm64: dts: imx8mp: don't initialize audio clocks from CCM node arm64: dts: imx8mm-venice: Fix GSC vdd_bat data size. arm64: dts: imx8mp: Add coresight trace components arm64: dts: imx93: add ddr performance monitor node arm64: dts: imx8mm-phg: Add display support arm64: dts: tqma8mqml: Add vcc supply to i2c eeproms arm64: dts: imx8mm-evk: Add HDMI support arm64: dts: imx8mn-var-som-symphony: adapt FEC pinctrl for SOMs with onboard PHY arm64: dts: imx8mn-var-som: add 20ms delay to ethernet regulator enable arm64: dts: imx8mp-msc-sm2s: Add sound card arm64: dts: imx8mn-beacon: Migrate sound card to simple-audio-card arm64: dts: imx8mp-beacon-kit: Enable WM8962 Audio CODEC arm64: dts: imx93: add fsl,stop-mode property to support WOL ... Link: https://lore.kernel.org/r/20230610072530.418847-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents f50a4e5 + 8e2facf commit 70cdf5e

41 files changed

Lines changed: 2727 additions & 118 deletions

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arch/arm64/boot/dts/freescale/Makefile

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@@ -54,7 +54,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
5454
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
5555
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
5656
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
57+
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb
5758
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
59+
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb
5860
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
5961
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
6062
dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb
@@ -99,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
99101
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
100102
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
101103
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

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cluster0_l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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CPU_PW20: cpu-pw20 {

arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

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cluster0_l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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CPU_PW20: cpu-pw20 {

arch/arm64/boot/dts/freescale/imx8dxl.dtsi

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A35_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Emtop Embedded Solutions
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*/
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/dts-v1/;
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#include "imx8mm-emtop-som.dtsi"
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/ {
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model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1";
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compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som",
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"fsl,imx8mm";
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};
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Emtop Embedded Solutions
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/usb/pd.h>
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#include "imx8mm.dtsi"
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/ {
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model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";
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compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";
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chosen {
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stdout-path = &uart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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led-0 {
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function = LED_FUNCTION_POWER;
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_EDGE_RISING>;
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regulators {
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buck1: BUCK1 {
67+
regulator-name = "BUCK1";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck3: BUCK3 {
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regulator-name = "BUCK3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4: BUCK4 {
93+
regulator-name = "BUCK4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3600000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
101+
regulator-name = "BUCK5";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
117+
regulator-name = "LDO1";
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regulator-min-microvolt = <1650000>;
119+
regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2: LDO2 {
125+
regulator-name = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <945000>;
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regulator-boot-on;
129+
regulator-always-on;
130+
};
131+
132+
ldo3: LDO3 {
133+
regulator-name = "LDO3";
134+
regulator-min-microvolt = <1710000>;
135+
regulator-max-microvolt = <1890000>;
136+
regulator-boot-on;
137+
regulator-always-on;
138+
};
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ldo4: LDO4 {
141+
regulator-name = "LDO4";
142+
regulator-min-microvolt = <810000>;
143+
regulator-max-microvolt = <945000>;
144+
regulator-boot-on;
145+
regulator-always-on;
146+
};
147+
148+
ldo5: LDO5 {
149+
regulator-name = "LDO5";
150+
regulator-min-microvolt = <1650000>;
151+
regulator-max-microvolt = <3600000>;
152+
};
153+
};
154+
};
155+
};
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157+
&uart2 {
158+
pinctrl-names = "default";
159+
pinctrl-0 = <&pinctrl_uart2>;
160+
status = "okay";
161+
};
162+
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&usdhc3 {
164+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
165+
pinctrl-0 = <&pinctrl_usdhc3>;
166+
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
167+
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
168+
bus-width = <8>;
169+
non-removable;
170+
status = "okay";
171+
};
172+
173+
&wdog1 {
174+
pinctrl-names = "default";
175+
pinctrl-0 = <&pinctrl_wdog>;
176+
fsl,ext-reset-output;
177+
status = "okay";
178+
};
179+
180+
&iomuxc {
181+
pinctrl_gpio_led: emtop-gpio-led-grp {
182+
fsl,pins = <
183+
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
184+
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
185+
>;
186+
};
187+
188+
pinctrl_i2c1: emtop-i2c1-grp {
189+
fsl,pins = <
190+
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
191+
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
192+
>;
193+
};
194+
195+
pinctrl_pmic: emtop-pmic-grp {
196+
fsl,pins = <
197+
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
198+
>;
199+
};
200+
201+
pinctrl_uart2: emtop-uart2-grp {
202+
fsl,pins = <
203+
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
204+
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
205+
>;
206+
};
207+
208+
pinctrl_usdhc3: emtop-usdhc3-grp {
209+
fsl,pins = <
210+
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
211+
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
212+
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
213+
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
214+
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
215+
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
216+
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
217+
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
218+
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
219+
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
220+
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
221+
>;
222+
};
223+
224+
pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp {
225+
fsl,pins = <
226+
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
227+
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
228+
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
229+
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
230+
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
231+
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
232+
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
233+
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
234+
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
235+
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
236+
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
237+
>;
238+
};
239+
240+
pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp {
241+
fsl,pins = <
242+
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
243+
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
244+
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
245+
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
246+
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
247+
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
248+
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
249+
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
250+
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
251+
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
252+
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
253+
>;
254+
};
255+
256+
pinctrl_wdog: emtop-wdog-grp {
257+
fsl,pins = <
258+
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
259+
>;
260+
};
261+
};

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