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1 parent df13676 commit 720452aCopy full SHA for 720452a
2 files changed
drivers/clk/microchip/Kconfig
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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config COMMON_CLK_PIC32
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- def_bool (COMMON_CLK && MACH_PIC32) || COMPILE_TEST
+ def_bool COMMON_CLK && MACH_PIC32
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config MCHP_CLK_MPFS
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bool "Clk driver for PolarFire SoC"
drivers/clk/microchip/clk-core.c
@@ -75,7 +75,6 @@
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/* SoC specific clock needed during SPLL clock rate switch */
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static struct clk_hw *pic32_sclk_hw;
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-#ifdef CONFIG_MATCH_PIC32
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/* add instruction pipeline delay while CPU clock is in-transition. */
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#define cpu_nop5() \
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do { \
@@ -85,9 +84,6 @@ do { \
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__asm__ __volatile__("nop"); \
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} while (0)
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-#else
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-#define cpu_nop5()
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-#endif
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/* Perpheral bus clocks */
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struct pic32_periph_clk {
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