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cristiccvinodkoul
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phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode
When making use of the clock provider functionality, the output clock does normally match the TMDS character rate, which is what the PHY PLL gets configured to. However, this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output_clock_rate = tmds_char_rate * 8 / bpc Since the existence of the clock divider wasn't taken into account when support for high bpc has been introduced, make the necessary adjustments to report the correct clock rate. Fixes: 9d0ec51 ("phy: rockchip: samsung-hdptx: Add high color depth management") Reported-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-1-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Lines changed: 8 additions & 6 deletions

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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1037,7 +1037,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
10371037

10381038
ret = rk_hdptx_post_enable_pll(hdptx);
10391039
if (!ret)
1040-
hdptx->hw_rate = hdptx->hdmi_cfg.tmds_char_rate;
1040+
hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
1041+
hdptx->hdmi_cfg.bpc);
10411042

10421043
return ret;
10431044
}
@@ -1895,19 +1896,20 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
18951896
* hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with
18961897
* a different rate argument.
18971898
*/
1898-
return hdptx->hdmi_cfg.tmds_char_rate;
1899+
return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->hdmi_cfg.bpc);
18991900
}
19001901

19011902
static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
19021903
unsigned long parent_rate)
19031904
{
19041905
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1906+
unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
19051907

19061908
/* Revert any unlikely TMDS char rate change since round_rate() */
1907-
if (hdptx->hdmi_cfg.tmds_char_rate != rate) {
1908-
dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\n",
1909-
rate, hdptx->hdmi_cfg.tmds_char_rate);
1910-
hdptx->hdmi_cfg.tmds_char_rate = rate;
1909+
if (hdptx->hdmi_cfg.tmds_char_rate != tmds_rate) {
1910+
dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n",
1911+
tmds_rate, hdptx->hdmi_cfg.tmds_char_rate);
1912+
hdptx->hdmi_cfg.tmds_char_rate = tmds_rate;
19111913
}
19121914

19131915
/*

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