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mtk-rex-bc-chenbebarino
mtk-rex-bc-chen
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clk: mediatek: reset: Support nonsequence base offsets of reset registers
The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent 2d2a290 commit 723e367

15 files changed

Lines changed: 85 additions & 43 deletions

‎drivers/clk/mediatek/clk-mt2701-eth.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,12 @@ static const struct mtk_gate eth_clks[] = {
3636
GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
3737
};
3838

39+
static u16 rst_ofs[] = { 0x34, };
40+
3941
static const struct mtk_clk_rst_desc clk_rst_desc = {
4042
.version = MTK_RST_SIMPLE,
41-
.rst_bank_nr = 1,
42-
.reg_ofs = 0x34,
43+
.rst_bank_ofs = rst_ofs,
44+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
4345
};
4446

4547
static const struct of_device_id of_match_clk_mt2701_eth[] = {

‎drivers/clk/mediatek/clk-mt2701-g3d.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] = {
3535
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
3636
};
3737

38+
static u16 rst_ofs[] = { 0xc, };
39+
3840
static const struct mtk_clk_rst_desc clk_rst_desc = {
3941
.version = MTK_RST_SIMPLE,
40-
.rst_bank_nr = 1,
41-
.reg_ofs = 0xc,
42+
.rst_bank_ofs = rst_ofs,
43+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
4244
};
4345

4446
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)

‎drivers/clk/mediatek/clk-mt2701-hif.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,12 @@ static const struct mtk_gate hif_clks[] = {
3333
GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
3434
};
3535

36+
static u16 rst_ofs[] = { 0x34, };
37+
3638
static const struct mtk_clk_rst_desc clk_rst_desc = {
3739
.version = MTK_RST_SIMPLE,
38-
.rst_bank_nr = 1,
39-
.reg_ofs = 0x34,
40+
.rst_bank_ofs = rst_ofs,
41+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
4042
};
4143

4244
static const struct of_device_id of_match_clk_mt2701_hif[] = {

‎drivers/clk/mediatek/clk-mt2701.c‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
735735
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
736736
};
737737

738+
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
739+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
740+
738741
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
739742
/* infrasys */
740743
{
741744
.version = MTK_RST_SIMPLE,
742-
.rst_bank_nr = 2,
743-
.reg_ofs = 0x30,
745+
.rst_bank_ofs = infrasys_rst_ofs,
746+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
744747
},
745748
/* pericfg */
746749
{
747750
.version = MTK_RST_SIMPLE,
748-
.rst_bank_nr = 2,
749-
.reg_ofs = 0x0,
751+
.rst_bank_ofs = pericfg_rst_ofs,
752+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
750753
},
751754
};
752755

‎drivers/clk/mediatek/clk-mt2712.c‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = {
12581258
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
12591259
};
12601260

1261+
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
1262+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
1263+
12611264
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
12621265
/* infra */
12631266
{
12641267
.version = MTK_RST_SIMPLE,
1265-
.rst_bank_nr = 2,
1266-
.reg_ofs = 0x30,
1268+
.rst_bank_ofs = infrasys_rst_ofs,
1269+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
12671270
},
12681271
/* peri */
12691272
{
12701273
.version = MTK_RST_SIMPLE,
1271-
.rst_bank_nr = 2,
1272-
.reg_ofs = 0x0,
1274+
.rst_bank_ofs = pericfg_rst_ofs,
1275+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
12731276
},
12741277
};
12751278

‎drivers/clk/mediatek/clk-mt7622-eth.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,10 +65,12 @@ static const struct mtk_gate sgmii_clks[] = {
6565
"ssusb_cdr_fb", 5),
6666
};
6767

68+
static u16 rst_ofs[] = { 0x34, };
69+
6870
static const struct mtk_clk_rst_desc clk_rst_desc = {
6971
.version = MTK_RST_SIMPLE,
70-
.rst_bank_nr = 1,
71-
.reg_ofs = 0x34,
72+
.rst_bank_ofs = rst_ofs,
73+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
7274
};
7375

7476
static int clk_mt7622_ethsys_init(struct platform_device *pdev)

‎drivers/clk/mediatek/clk-mt7622-hif.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,10 +76,12 @@ static const struct mtk_gate pcie_clks[] = {
7676
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
7777
};
7878

79+
static u16 rst_ofs[] = { 0x34, };
80+
7981
static const struct mtk_clk_rst_desc clk_rst_desc = {
8082
.version = MTK_RST_SIMPLE,
81-
.rst_bank_nr = 1,
82-
.reg_ofs = 0x34,
83+
.rst_bank_ofs = rst_ofs,
84+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
8385
};
8486

8587
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)

‎drivers/clk/mediatek/clk-mt7622.c‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -610,18 +610,21 @@ static struct mtk_composite peri_muxes[] = {
610610
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
611611
};
612612

613+
static u16 infrasys_rst_ofs[] = { 0x30, };
614+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
615+
613616
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
614617
/* infrasys */
615618
{
616619
.version = MTK_RST_SIMPLE,
617-
.rst_bank_nr = 1,
618-
.reg_ofs = 0x30,
620+
.rst_bank_ofs = infrasys_rst_ofs,
621+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
619622
},
620623
/* pericfg */
621624
{
622625
.version = MTK_RST_SIMPLE,
623-
.rst_bank_nr = 2,
624-
.reg_ofs = 0x0,
626+
.rst_bank_ofs = pericfg_rst_ofs,
627+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
625628
},
626629
};
627630

‎drivers/clk/mediatek/clk-mt7629-eth.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,10 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = {
7676
}
7777
};
7878

79+
static u16 rst_ofs[] = { 0x34, };
80+
7981
static const struct mtk_clk_rst_desc clk_rst_desc = {
8082
.version = MTK_RST_SIMPLE,
81-
.rst_bank_nr = 1,
82-
.reg_ofs = 0x34,
83+
.rst_bank_ofs = rst_ofs,
84+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
8385
};
8486

8587
static int clk_mt7629_ethsys_init(struct platform_device *pdev)

‎drivers/clk/mediatek/clk-mt7629-hif.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,12 @@ static const struct mtk_gate pcie_clks[] = {
7171
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
7272
};
7373

74+
static u16 rst_ofs[] = { 0x34, };
75+
7476
static const struct mtk_clk_rst_desc clk_rst_desc = {
7577
.version = MTK_RST_SIMPLE,
76-
.rst_bank_nr = 1,
77-
.reg_ofs = 0x34,
78+
.rst_bank_ofs = rst_ofs,
79+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
7880
};
7981

8082
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)

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