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Jack Xiaoalexdeucher
Jack Xiao
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alexdeucher
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drm/amdgpu/mes12: configure two pipes hardware resources
Configure two pipes with different hardware resources. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ea5d6db)
1 parent 1097727 commit 7254027

4 files changed

Lines changed: 81 additions & 64 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c‎

Lines changed: 47 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -165,36 +165,38 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
165165
adev->mes.sdma_hqd_mask[i] = 0xfc;
166166
}
167167

168-
r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs);
169-
if (r) {
170-
dev_err(adev->dev,
171-
"(%d) ring trail_fence_offs wb alloc failed\n", r);
172-
goto error_ids;
173-
}
174-
adev->mes.sch_ctx_gpu_addr =
175-
adev->wb.gpu_addr + (adev->mes.sch_ctx_offs * 4);
176-
adev->mes.sch_ctx_ptr =
177-
(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs];
168+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
169+
r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]);
170+
if (r) {
171+
dev_err(adev->dev,
172+
"(%d) ring trail_fence_offs wb alloc failed\n",
173+
r);
174+
goto error;
175+
}
176+
adev->mes.sch_ctx_gpu_addr[i] =
177+
adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4);
178+
adev->mes.sch_ctx_ptr[i] =
179+
(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]];
178180

179-
r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs);
180-
if (r) {
181-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
182-
dev_err(adev->dev,
183-
"(%d) query_status_fence_offs wb alloc failed\n", r);
184-
goto error_ids;
181+
r = amdgpu_device_wb_get(adev,
182+
&adev->mes.query_status_fence_offs[i]);
183+
if (r) {
184+
dev_err(adev->dev,
185+
"(%d) query_status_fence_offs wb alloc failed\n",
186+
r);
187+
goto error;
188+
}
189+
adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr +
190+
(adev->mes.query_status_fence_offs[i] * 4);
191+
adev->mes.query_status_fence_ptr[i] =
192+
(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]];
185193
}
186-
adev->mes.query_status_fence_gpu_addr =
187-
adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4);
188-
adev->mes.query_status_fence_ptr =
189-
(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs];
190194

191195
r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs);
192196
if (r) {
193-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
194-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
195197
dev_err(adev->dev,
196198
"(%d) read_val_offs alloc failed\n", r);
197-
goto error_ids;
199+
goto error;
198200
}
199201
adev->mes.read_val_gpu_addr =
200202
adev->wb.gpu_addr + (adev->mes.read_val_offs * 4);
@@ -214,10 +216,16 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
214216
error_doorbell:
215217
amdgpu_mes_doorbell_free(adev);
216218
error:
217-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
218-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
219-
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
220-
error_ids:
219+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
220+
if (adev->mes.sch_ctx_ptr[i])
221+
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
222+
if (adev->mes.query_status_fence_ptr[i])
223+
amdgpu_device_wb_free(adev,
224+
adev->mes.query_status_fence_offs[i]);
225+
}
226+
if (adev->mes.read_val_ptr)
227+
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
228+
221229
idr_destroy(&adev->mes.pasid_idr);
222230
idr_destroy(&adev->mes.gang_id_idr);
223231
idr_destroy(&adev->mes.queue_id_idr);
@@ -228,13 +236,22 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
228236

229237
void amdgpu_mes_fini(struct amdgpu_device *adev)
230238
{
239+
int i;
240+
231241
amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj,
232242
&adev->mes.event_log_gpu_addr,
233243
&adev->mes.event_log_cpu_addr);
234244

235-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
236-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
237-
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
245+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
246+
if (adev->mes.sch_ctx_ptr[i])
247+
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
248+
if (adev->mes.query_status_fence_ptr[i])
249+
amdgpu_device_wb_free(adev,
250+
adev->mes.query_status_fence_offs[i]);
251+
}
252+
if (adev->mes.read_val_ptr)
253+
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
254+
238255
amdgpu_mes_doorbell_free(adev);
239256

240257
idr_destroy(&adev->mes.pasid_idr);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -112,12 +112,12 @@ struct amdgpu_mes {
112112
uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
113113
uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
114114
uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
115-
uint32_t sch_ctx_offs;
116-
uint64_t sch_ctx_gpu_addr;
117-
uint64_t *sch_ctx_ptr;
118-
uint32_t query_status_fence_offs;
119-
uint64_t query_status_fence_gpu_addr;
120-
uint64_t *query_status_fence_ptr;
115+
uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
116+
uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
117+
uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
118+
uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
119+
uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
120+
uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];
121121
uint32_t read_val_offs;
122122
uint64_t read_val_gpu_addr;
123123
uint32_t *read_val_ptr;

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -522,9 +522,9 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
522522
mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
523523
mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
524524
mes_set_hw_res_pkt.paging_vmid = 0;
525-
mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
525+
mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0];
526526
mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
527-
mes->query_status_fence_gpu_addr;
527+
mes->query_status_fence_gpu_addr[0];
528528

529529
for (i = 0; i < MAX_COMPUTE_PIPES; i++)
530530
mes_set_hw_res_pkt.compute_hqd_mask[i] =
@@ -1210,9 +1210,6 @@ static int mes_v11_0_sw_fini(void *handle)
12101210
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
12111211
int pipe;
12121212

1213-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1214-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1215-
12161213
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
12171214
kfree(adev->mes.mqd_backup[pipe]);
12181215

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c‎

Lines changed: 26 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -542,27 +542,33 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
542542
mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
543543
mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
544544

545-
mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
546-
mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
547-
mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
548-
mes_set_hw_res_pkt.paging_vmid = 0;
549-
mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
550-
mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
551-
mes->query_status_fence_gpu_addr;
552-
553-
for (i = 0; i < MAX_COMPUTE_PIPES; i++)
554-
mes_set_hw_res_pkt.compute_hqd_mask[i] =
555-
mes->compute_hqd_mask[i];
556-
557-
for (i = 0; i < MAX_GFX_PIPES; i++)
558-
mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
559-
560-
for (i = 0; i < MAX_SDMA_PIPES; i++)
561-
mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
545+
if (pipe == AMDGPU_MES_SCHED_PIPE) {
546+
mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
547+
mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
548+
mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
549+
mes_set_hw_res_pkt.paging_vmid = 0;
550+
551+
for (i = 0; i < MAX_COMPUTE_PIPES; i++)
552+
mes_set_hw_res_pkt.compute_hqd_mask[i] =
553+
mes->compute_hqd_mask[i];
554+
555+
for (i = 0; i < MAX_GFX_PIPES; i++)
556+
mes_set_hw_res_pkt.gfx_hqd_mask[i] =
557+
mes->gfx_hqd_mask[i];
558+
559+
for (i = 0; i < MAX_SDMA_PIPES; i++)
560+
mes_set_hw_res_pkt.sdma_hqd_mask[i] =
561+
mes->sdma_hqd_mask[i];
562+
563+
for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
564+
mes_set_hw_res_pkt.aggregated_doorbells[i] =
565+
mes->aggregated_doorbells[i];
566+
}
562567

563-
for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
564-
mes_set_hw_res_pkt.aggregated_doorbells[i] =
565-
mes->aggregated_doorbells[i];
568+
mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =
569+
mes->sch_ctx_gpu_addr[pipe];
570+
mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
571+
mes->query_status_fence_gpu_addr[pipe];
566572

567573
for (i = 0; i < 5; i++) {
568574
mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
@@ -1292,9 +1298,6 @@ static int mes_v12_0_sw_fini(void *handle)
12921298
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
12931299
int pipe;
12941300

1295-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1296-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1297-
12981301
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
12991302
kfree(adev->mes.mqd_backup[pipe]);
13001303

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