Skip to content

Commit 72f3542

Browse files
torvaldstorvalds
committed
Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Fix out-of-sync IVs in self-test for IPsec AEAD algorithms Algorithms: - Use formally verified implementation of x86/curve25519 Drivers: - Enhance hwrng support in caam - Use crypto_engine for skcipher/aead/rsa/hash in caam - Add Xilinx AES driver - Add uacce driver - Register zip engine to uacce in hisilicon - Add support for OCTEON TX CPT engine in marvell" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (162 commits) crypto: af_alg - bool type cosmetics crypto: arm[64]/poly1305 - add artifact to .gitignore files crypto: caam - limit single JD RNG output to maximum of 16 bytes crypto: caam - enable prediction resistance in HRWNG bus: fsl-mc: add api to retrieve mc version crypto: caam - invalidate entropy register during RNG initialization crypto: caam - check if RNG job failed crypto: caam - simplify RNG implementation crypto: caam - drop global context pointer and init_done crypto: caam - use struct hwrng's .init for initialization crypto: caam - allocate RNG instantiation descriptor with GFP_DMA crypto: ccree - remove duplicated include from cc_aead.c crypto: chelsio - remove set but not used variable 'adap' crypto: marvell - enable OcteonTX cpt options for build crypto: marvell - add the Virtual Function driver for CPT crypto: marvell - add support for OCTEON TX CPT engine crypto: marvell - create common Kconfig and Makefile for Marvell crypto: arm/neon - memzero_explicit aes-cbc key crypto: bcm - Use scnprintf() for avoiding potential buffer overflow crypto: atmel-i2c - Fix wakeup fail ...
2 parents 890f0b0 + fcb90d5 commit 72f3542

152 files changed

Lines changed: 13777 additions & 5297 deletions

File tree

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/ABI/testing/sysfs-driver-uacce‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
What: /sys/class/uacce/<dev_name>/api
2+
Date: Feb 2020
3+
KernelVersion: 5.7
4+
Contact: linux-accelerators@lists.ozlabs.org
5+
Description: Api of the device
6+
Can be any string and up to userspace to parse.
7+
Application use the api to match the correct driver
8+
9+
What: /sys/class/uacce/<dev_name>/flags
10+
Date: Feb 2020
11+
KernelVersion: 5.7
12+
Contact: linux-accelerators@lists.ozlabs.org
13+
Description: Attributes of the device, see UACCE_DEV_xxx flag defined in uacce.h
14+
15+
What: /sys/class/uacce/<dev_name>/available_instances
16+
Date: Feb 2020
17+
KernelVersion: 5.7
18+
Contact: linux-accelerators@lists.ozlabs.org
19+
Description: Available instances left of the device
20+
Return -ENODEV if uacce_ops get_available_instances is not provided
21+
22+
What: /sys/class/uacce/<dev_name>/algorithms
23+
Date: Feb 2020
24+
KernelVersion: 5.7
25+
Contact: linux-accelerators@lists.ozlabs.org
26+
Description: Algorithms supported by this accelerator, separated by new line.
27+
Can be any string and up to userspace to parse.
28+
29+
What: /sys/class/uacce/<dev_name>/region_mmio_size
30+
Date: Feb 2020
31+
KernelVersion: 5.7
32+
Contact: linux-accelerators@lists.ozlabs.org
33+
Description: Size (bytes) of mmio region queue file
34+
35+
What: /sys/class/uacce/<dev_name>/region_dus_size
36+
Date: Feb 2020
37+
KernelVersion: 5.7
38+
Contact: linux-accelerators@lists.ozlabs.org
39+
Description: Size (bytes) of dus region queue file

‎Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
8+
9+
maintainers:
10+
- Kalyani Akula <kalyani.akula@xilinx.com>
11+
- Michal Simek <michal.simek@xilinx.com>
12+
13+
description: |
14+
The ZynqMP AES-GCM hardened cryptographic accelerator is used to
15+
encrypt or decrypt the data with provided key and initialization vector.
16+
17+
properties:
18+
compatible:
19+
const: xlnx,zynqmp-aes
20+
21+
required:
22+
- compatible
23+
24+
additionalProperties: false
25+
26+
examples:
27+
- |
28+
firmware {
29+
zynqmp_firmware: zynqmp-firmware {
30+
compatible = "xlnx,zynqmp-firmware";
31+
method = "smc";
32+
xlnx_aes: zynqmp-aes {
33+
compatible = "xlnx,zynqmp-aes";
34+
};
35+
};
36+
};
37+
...

‎Documentation/misc-devices/uacce.rst‎

Lines changed: 176 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,176 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
Introduction of Uacce
4+
---------------------
5+
6+
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
7+
provide Shared Virtual Addressing (SVA) between accelerators and processes.
8+
So accelerator can access any data structure of the main cpu.
9+
This differs from the data sharing between cpu and io device, which share
10+
only data content rather than address.
11+
Because of the unified address, hardware and user space of process can
12+
share the same virtual address in the communication.
13+
Uacce takes the hardware accelerator as a heterogeneous processor, while
14+
IOMMU share the same CPU page tables and as a result the same translation
15+
from va to pa.
16+
17+
::
18+
19+
__________________________ __________________________
20+
| | | |
21+
| User application (CPU) | | Hardware Accelerator |
22+
|__________________________| |__________________________|
23+
24+
| |
25+
| va | va
26+
V V
27+
__________ __________
28+
| | | |
29+
| MMU | | IOMMU |
30+
|__________| |__________|
31+
| |
32+
| |
33+
V pa V pa
34+
_______________________________________
35+
| |
36+
| Memory |
37+
|_______________________________________|
38+
39+
40+
41+
Architecture
42+
------------
43+
44+
Uacce is the kernel module, taking charge of iommu and address sharing.
45+
The user drivers and libraries are called WarpDrive.
46+
47+
The uacce device, built around the IOMMU SVA API, can access multiple
48+
address spaces, including the one without PASID.
49+
50+
A virtual concept, queue, is used for the communication. It provides a
51+
FIFO-like interface. And it maintains a unified address space between the
52+
application and all involved hardware.
53+
54+
::
55+
56+
___________________ ________________
57+
| | user API | |
58+
| WarpDrive library | ------------> | user driver |
59+
|___________________| |________________|
60+
| |
61+
| |
62+
| queue fd |
63+
| |
64+
| |
65+
v |
66+
___________________ _________ |
67+
| | | | | mmap memory
68+
| Other framework | | uacce | | r/w interface
69+
| crypto/nic/others | |_________| |
70+
|___________________| |
71+
| | |
72+
| register | register |
73+
| | |
74+
| | |
75+
| _________________ __________ |
76+
| | | | | |
77+
------------- | Device Driver | | IOMMU | |
78+
|_________________| |__________| |
79+
| |
80+
| V
81+
| ___________________
82+
| | |
83+
-------------------------- | Device(Hardware) |
84+
|___________________|
85+
86+
87+
How does it work
88+
----------------
89+
90+
Uacce uses mmap and IOMMU to play the trick.
91+
92+
Uacce creates a chrdev for every device registered to it. New queue is
93+
created when user application open the chrdev. The file descriptor is used
94+
as the user handle of the queue.
95+
The accelerator device present itself as an Uacce object, which exports as
96+
a chrdev to the user space. The user application communicates with the
97+
hardware by ioctl (as control path) or share memory (as data path).
98+
99+
The control path to the hardware is via file operation, while data path is
100+
via mmap space of the queue fd.
101+
102+
The queue file address space:
103+
104+
::
105+
106+
/**
107+
* enum uacce_qfrt: qfrt type
108+
* @UACCE_QFRT_MMIO: device mmio region
109+
* @UACCE_QFRT_DUS: device user share region
110+
*/
111+
enum uacce_qfrt {
112+
UACCE_QFRT_MMIO = 0,
113+
UACCE_QFRT_DUS = 1,
114+
};
115+
116+
All regions are optional and differ from device type to type.
117+
Each region can be mmapped only once, otherwise -EEXIST returns.
118+
119+
The device mmio region is mapped to the hardware mmio space. It is generally
120+
used for doorbell or other notification to the hardware. It is not fast enough
121+
as data channel.
122+
123+
The device user share region is used for share data buffer between user process
124+
and device.
125+
126+
127+
The Uacce register API
128+
----------------------
129+
130+
The register API is defined in uacce.h.
131+
132+
::
133+
134+
struct uacce_interface {
135+
char name[UACCE_MAX_NAME_SIZE];
136+
unsigned int flags;
137+
const struct uacce_ops *ops;
138+
};
139+
140+
According to the IOMMU capability, uacce_interface flags can be:
141+
142+
::
143+
144+
/**
145+
* UACCE Device flags:
146+
* UACCE_DEV_SVA: Shared Virtual Addresses
147+
* Support PASID
148+
* Support device page faults (PCI PRI or SMMU Stall)
149+
*/
150+
#define UACCE_DEV_SVA BIT(0)
151+
152+
struct uacce_device *uacce_alloc(struct device *parent,
153+
struct uacce_interface *interface);
154+
int uacce_register(struct uacce_device *uacce);
155+
void uacce_remove(struct uacce_device *uacce);
156+
157+
uacce_register results can be:
158+
159+
a. If uacce module is not compiled, ERR_PTR(-ENODEV)
160+
161+
b. Succeed with the desired flags
162+
163+
c. Succeed with the negotiated flags, for example
164+
165+
uacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA
166+
167+
So user driver need check return value as well as the negotiated uacce->flags.
168+
169+
170+
The user driver
171+
---------------
172+
173+
The queue file mmap space will need a user driver to wrap the communication
174+
protocol. Uacce provides some attributes in sysfs for the user driver to
175+
match the right accelerator accordingly.
176+
More details in Documentation/ABI/testing/sysfs-driver-uacce.

‎MAINTAINERS‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4577,7 +4577,9 @@ S: Supported
45774577
F: drivers/scsi/cxgbi/cxgb3i
45784578

45794579
CXGB4 CRYPTO DRIVER (chcr)
4580-
M: Atul Gupta <atul.gupta@chelsio.com>
4580+
M: Ayush Sawal <ayush.sawal@chelsio.com>
4581+
M: Vinay Kumar Yadav <vinay.yadav@chelsio.com>
4582+
M: Rohit Maheshwari <rohitm@chelsio.com>
45814583
L: linux-crypto@vger.kernel.org
45824584
W: http://www.chelsio.com
45834585
S: Supported
@@ -10066,6 +10068,7 @@ F: Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
1006610068
MARVELL CRYPTO DRIVER
1006710069
M: Boris Brezillon <bbrezillon@kernel.org>
1006810070
M: Arnaud Ebalard <arno@natisbad.org>
10071+
M: Srujana Challa <schalla@marvell.com>
1006910072
F: drivers/crypto/marvell/
1007010073
S: Maintained
1007110074
L: linux-crypto@vger.kernel.org
@@ -17139,6 +17142,18 @@ W: http://linuxtv.org
1713917142
S: Maintained
1714017143
F: drivers/media/pci/tw686x/
1714117144

17145+
UACCE ACCELERATOR FRAMEWORK
17146+
M: Zhangfei Gao <zhangfei.gao@linaro.org>
17147+
M: Zhou Wang <wangzhou1@hisilicon.com>
17148+
L: linux-accelerators@lists.ozlabs.org
17149+
L: linux-kernel@vger.kernel.org
17150+
S: Maintained
17151+
F: Documentation/ABI/testing/sysfs-driver-uacce
17152+
F: Documentation/misc-devices/uacce.rst
17153+
F: drivers/misc/uacce/
17154+
F: include/linux/uacce.h
17155+
F: include/uapi/misc/uacce/
17156+
1714217157
UBI FILE SYSTEM (UBIFS)
1714317158
M: Richard Weinberger <richard@nod.at>
1714417159
L: linux-mtd@lists.infradead.org

‎arch/arm/crypto/.gitignore‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
11
aesbs-core.S
22
sha256-core.S
33
sha512-core.S
4+
poly1305-core.S

‎arch/arm/crypto/aes-neonbs-glue.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,7 @@ static int aesbs_cbc_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
138138
kernel_neon_begin();
139139
aesbs_convert_key(ctx->key.rk, rk.key_enc, ctx->key.rounds);
140140
kernel_neon_end();
141+
memzero_explicit(&rk, sizeof(rk));
141142

142143
return crypto_cipher_setkey(ctx->enc_tfm, in_key, key_len);
143144
}

‎arch/arm/crypto/ghash-ce-core.S‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,9 @@
88
#include <linux/linkage.h>
99
#include <asm/assembler.h>
1010

11+
.arch armv8-a
12+
.fpu crypto-neon-fp-armv8
13+
1114
SHASH .req q0
1215
T1 .req q1
1316
XL .req q2
@@ -88,8 +91,6 @@
8891
T3_H .req d17
8992

9093
.text
91-
.arch armv8-a
92-
.fpu crypto-neon-fp-armv8
9394

9495
.macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4
9596
vmull.p64 \rd, \rn, \rm

‎arch/arm64/crypto/.gitignore‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,3 @@
11
sha256-core.S
22
sha512-core.S
3+
poly1305-core.S

‎arch/arm64/crypto/aes-neonbs-glue.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ static int aesbs_cbc_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
151151
kernel_neon_begin();
152152
aesbs_convert_key(ctx->key.rk, rk.key_enc, ctx->key.rounds);
153153
kernel_neon_end();
154+
memzero_explicit(&rk, sizeof(rk));
154155

155156
return 0;
156157
}

‎arch/arm64/crypto/sha1-ce-glue.c‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,12 +91,32 @@ static int sha1_ce_final(struct shash_desc *desc, u8 *out)
9191
return sha1_base_finish(desc, out);
9292
}
9393

94+
static int sha1_ce_export(struct shash_desc *desc, void *out)
95+
{
96+
struct sha1_ce_state *sctx = shash_desc_ctx(desc);
97+
98+
memcpy(out, &sctx->sst, sizeof(struct sha1_state));
99+
return 0;
100+
}
101+
102+
static int sha1_ce_import(struct shash_desc *desc, const void *in)
103+
{
104+
struct sha1_ce_state *sctx = shash_desc_ctx(desc);
105+
106+
memcpy(&sctx->sst, in, sizeof(struct sha1_state));
107+
sctx->finalize = 0;
108+
return 0;
109+
}
110+
94111
static struct shash_alg alg = {
95112
.init = sha1_base_init,
96113
.update = sha1_ce_update,
97114
.final = sha1_ce_final,
98115
.finup = sha1_ce_finup,
116+
.import = sha1_ce_import,
117+
.export = sha1_ce_export,
99118
.descsize = sizeof(struct sha1_ce_state),
119+
.statesize = sizeof(struct sha1_state),
100120
.digestsize = SHA1_DIGEST_SIZE,
101121
.base = {
102122
.cra_name = "sha1",

0 commit comments

Comments
 (0)