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Merge tag 'v6.4-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Total usage stats now include all that returned errors (instead of just some) - Remove maximum hash statesize limit - Add cloning support for hmac and unkeyed hashes - Demote BUG_ON in crypto_unregister_alg to a WARN_ON Algorithms: - Use RIP-relative addressing on x86 to prepare for PIE build - Add accelerated AES/GCM stitched implementation on powerpc P10 - Add some test vectors for cmac(camellia) - Remove failure case where jent is unavailable outside of FIPS mode in drbg - Add permanent and intermittent health error checks in jitter RNG Drivers: - Add support for 402xx devices in qat - Add support for HiSTB TRNG - Fix hash concurrency issues in stm32 - Add OP-TEE firmware support in caam" * tag 'v6.4-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (139 commits) i2c: designware: Add doorbell support for Mendocino i2c: designware: Use PCI PSP driver for communication powerpc: Move Power10 feature PPC_MODULE_FEATURE_P10 crypto: p10-aes-gcm - Remove POWER10_CPU dependency crypto: testmgr - Add some test vectors for cmac(camellia) crypto: cryptd - Add support for cloning hashes crypto: cryptd - Convert hash to use modern init_tfm/exit_tfm crypto: hmac - Add support for cloning crypto: hash - Add crypto_clone_ahash/shash crypto: api - Add crypto_clone_tfm crypto: api - Add crypto_tfm_get crypto: x86/sha - Use local .L symbols for code crypto: x86/crc32 - Use local .L symbols for code crypto: x86/aesni - Use local .L symbols for code crypto: x86/sha256 - Use RIP-relative addressing crypto: x86/ghash - Use RIP-relative addressing crypto: x86/des3 - Use RIP-relative addressing crypto: x86/crc32c - Use RIP-relative addressing crypto: x86/cast6 - Use RIP-relative addressing crypto: x86/cast5 - Use RIP-relative addressing ...
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‎Documentation/devicetree/bindings/crypto/qcom-qce.txt‎

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This file was deleted.

‎Documentation/devicetree/bindings/crypto/qcom-qce.yaml‎

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@@ -0,0 +1,123 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm crypto engine driver
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maintainers:
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- Bhupesh Sharma <bhupesh.sharma@linaro.org>
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description:
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This document defines the binding for the QCE crypto
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controller found on Qualcomm parts.
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properties:
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compatible:
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oneOf:
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- const: qcom,crypto-v5.1
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deprecated: true
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description: Kept only for ABI backward compatibility
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- const: qcom,crypto-v5.4
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deprecated: true
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description: Kept only for ABI backward compatibility
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- items:
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- enum:
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- qcom,ipq6018-qce
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- qcom,ipq8074-qce
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- qcom,msm8996-qce
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- qcom,sdm845-qce
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- const: qcom,ipq4019-qce
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- const: qcom,qce
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- items:
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- enum:
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- qcom,sm8250-qce
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- qcom,sm8350-qce
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- qcom,sm8450-qce
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- qcom,sm8550-qce
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- const: qcom,sm8150-qce
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- const: qcom,qce
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reg:
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maxItems: 1
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clocks:
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items:
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- description: iface clocks register interface.
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- description: bus clocks data transfer interface.
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- description: core clocks rest of the crypto block.
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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iommus:
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minItems: 1
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maxItems: 8
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description:
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phandle to apps_smmu node with sid mask.
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interconnects:
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maxItems: 1
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description:
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Interconnect path between qce crypto and main memory.
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interconnect-names:
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const: memory
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dmas:
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items:
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- description: DMA specifiers for rx dma channel.
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- description: DMA specifiers for tx dma channel.
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dma-names:
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items:
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- const: rx
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- const: tx
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,crypto-v5.1
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- qcom,crypto-v5.4
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- qcom,ipq4019-qce
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then:
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required:
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- clocks
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- clock-names
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required:
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- compatible
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- reg
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- dmas
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- dma-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-apq8084.h>
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crypto-engine@fd45a000 {
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compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
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reg = <0xfd45a000 0x6000>;
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clocks = <&gcc GCC_CE2_AHB_CLK>,
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<&gcc GCC_CE2_AXI_CLK>,
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<&gcc GCC_CE2_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 2>, <&cryptobam 3>;
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dma-names = "rx", "tx";
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iommus = <&apps_smmu 0x584 0x0011>,
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<&apps_smmu 0x586 0x0011>,
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<&apps_smmu 0x594 0x0011>,
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<&apps_smmu 0x596 0x0011>;
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};

‎MAINTAINERS‎

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Original file line numberDiff line numberDiff line change
@@ -2269,7 +2269,7 @@ F: arch/arm/boot/dts/intel-ixp*
22692269
F: arch/arm/mach-ixp4xx/
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F: drivers/bus/intel-ixp4xx-eb.c
22712271
F: drivers/clocksource/timer-ixp4xx.c
2272-
F: drivers/crypto/ixp4xx_crypto.c
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F: drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
22732273
F: drivers/gpio/gpio-ixp4xx.c
22742274
F: drivers/irqchip/irq-ixp4xx.c
22752275

@@ -10391,7 +10391,7 @@ INTEL IXP4XX CRYPTO SUPPORT
1039110391
M: Corentin Labbe <clabbe@baylibre.com>
1039210392
L: linux-crypto@vger.kernel.org
1039310393
S: Maintained
10394-
F: drivers/crypto/ixp4xx_crypto.c
10394+
F: drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
1039510395

1039610396
INTEL ISHTP ECLITE DRIVER
1039710397
M: Sumesh K Naduvalath <sumesh.k.naduvalath@intel.com>
@@ -10426,32 +10426,32 @@ INTEL KEEM BAY OCS AES/SM4 CRYPTO DRIVER
1042610426
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
1042710427
S: Maintained
1042810428
F: Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml
10429-
F: drivers/crypto/keembay/Kconfig
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F: drivers/crypto/keembay/Makefile
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F: drivers/crypto/keembay/keembay-ocs-aes-core.c
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F: drivers/crypto/keembay/ocs-aes.c
10433-
F: drivers/crypto/keembay/ocs-aes.h
10429+
F: drivers/crypto/intel/keembay/Kconfig
10430+
F: drivers/crypto/intel/keembay/Makefile
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F: drivers/crypto/intel/keembay/keembay-ocs-aes-core.c
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F: drivers/crypto/intel/keembay/ocs-aes.c
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F: drivers/crypto/intel/keembay/ocs-aes.h
1043410434

1043510435
INTEL KEEM BAY OCS ECC CRYPTO DRIVER
1043610436
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
1043710437
M: Prabhjot Khurana <prabhjot.khurana@intel.com>
1043810438
M: Mark Gross <mgross@linux.intel.com>
1043910439
S: Maintained
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F: Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml
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F: drivers/crypto/keembay/Kconfig
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F: drivers/crypto/keembay/Makefile
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F: drivers/crypto/keembay/keembay-ocs-ecc.c
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F: drivers/crypto/intel/keembay/Kconfig
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F: drivers/crypto/intel/keembay/Makefile
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F: drivers/crypto/intel/keembay/keembay-ocs-ecc.c
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1044510445
INTEL KEEM BAY OCS HCU CRYPTO DRIVER
1044610446
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
1044710447
M: Declan Murphy <declan.murphy@intel.com>
1044810448
S: Maintained
1044910449
F: Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
10450-
F: drivers/crypto/keembay/Kconfig
10451-
F: drivers/crypto/keembay/Makefile
10452-
F: drivers/crypto/keembay/keembay-ocs-hcu-core.c
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F: drivers/crypto/keembay/ocs-hcu.c
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F: drivers/crypto/keembay/ocs-hcu.h
10450+
F: drivers/crypto/intel/keembay/Kconfig
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F: drivers/crypto/intel/keembay/Makefile
10452+
F: drivers/crypto/intel/keembay/keembay-ocs-hcu-core.c
10453+
F: drivers/crypto/intel/keembay/ocs-hcu.c
10454+
F: drivers/crypto/intel/keembay/ocs-hcu.h
1045510455

1045610456
INTEL THUNDER BAY EMMC PHY DRIVER
1045710457
M: Nandhini Srikandan <nandhini.srikandan@intel.com>
@@ -17027,7 +17027,7 @@ QAT DRIVER
1702717027
M: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
1702817028
L: qat-linux@intel.com
1702917029
S: Supported
17030-
F: drivers/crypto/qat/
17030+
F: drivers/crypto/intel/qat/
1703117031

1703217032
QCOM AUDIO (ASoC) DRIVERS
1703317033
M: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
@@ -17295,6 +17295,7 @@ M: Thara Gopinath <thara.gopinath@gmail.com>
1729517295
L: linux-crypto@vger.kernel.org
1729617296
L: linux-arm-msm@vger.kernel.org
1729717297
S: Maintained
17298+
F: Documentation/devicetree/bindings/crypto/qcom-qce.yaml
1729817299
F: drivers/crypto/qce/
1729917300

1730017301
QUALCOMM EMAC GIGABIT ETHERNET DRIVER

‎arch/arm64/boot/dts/qcom/sm8550.dtsi‎

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18501850
};
18511851

18521852
crypto: crypto@1de0000 {
1853-
compatible = "qcom,sm8550-qce";
1853+
compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
18541854
reg = <0x0 0x01dfa000 0x0 0x6000>;
18551855
dmas = <&cryptobam 4>, <&cryptobam 5>;
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dma-names = "rx", "tx";

‎arch/arm64/crypto/aes-neonbs-core.S‎

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*/
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1717
#include <linux/linkage.h>
18+
#include <linux/cfi_types.h>
1819
#include <asm/assembler.h>
1920

2021
.text
@@ -620,12 +621,12 @@ SYM_FUNC_END(aesbs_decrypt8)
620621
.endm
621622

622623
.align 4
623-
SYM_FUNC_START(aesbs_ecb_encrypt)
624+
SYM_TYPED_FUNC_START(aesbs_ecb_encrypt)
624625
__ecb_crypt aesbs_encrypt8, v0, v1, v4, v6, v3, v7, v2, v5
625626
SYM_FUNC_END(aesbs_ecb_encrypt)
626627

627628
.align 4
628-
SYM_FUNC_START(aesbs_ecb_decrypt)
629+
SYM_TYPED_FUNC_START(aesbs_ecb_decrypt)
629630
__ecb_crypt aesbs_decrypt8, v0, v1, v6, v4, v2, v7, v3, v5
630631
SYM_FUNC_END(aesbs_ecb_decrypt)
631632

@@ -799,11 +800,11 @@ SYM_FUNC_END(__xts_crypt8)
799800
ret
800801
.endm
801802

802-
SYM_FUNC_START(aesbs_xts_encrypt)
803+
SYM_TYPED_FUNC_START(aesbs_xts_encrypt)
803804
__xts_crypt aesbs_encrypt8, v0, v1, v4, v6, v3, v7, v2, v5
804805
SYM_FUNC_END(aesbs_xts_encrypt)
805806

806-
SYM_FUNC_START(aesbs_xts_decrypt)
807+
SYM_TYPED_FUNC_START(aesbs_xts_decrypt)
807808
__xts_crypt aesbs_decrypt8, v0, v1, v6, v4, v2, v7, v3, v5
808809
SYM_FUNC_END(aesbs_xts_decrypt)
809810

‎arch/powerpc/crypto/Kconfig‎

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@@ -94,4 +94,21 @@ config CRYPTO_AES_PPC_SPE
9494
architecture specific assembler implementations that work on 1KB
9595
tables or 256 bytes S-boxes.
9696

97+
config CRYPTO_AES_GCM_P10
98+
tristate "Stitched AES/GCM acceleration support on P10 or later CPU (PPC)"
99+
depends on PPC64 && CPU_LITTLE_ENDIAN
100+
select CRYPTO_LIB_AES
101+
select CRYPTO_ALGAPI
102+
select CRYPTO_AEAD
103+
default m
104+
help
105+
AEAD cipher: AES cipher algorithms (FIPS-197)
106+
GCM (Galois/Counter Mode) authenticated encryption mode (NIST SP800-38D)
107+
Architecture: powerpc64 using:
108+
- little-endian
109+
- Power10 or later features
110+
111+
Support for cryptographic acceleration instructions on Power10 or
112+
later CPU. This module supports stitched acceleration for AES/GCM.
113+
97114
endmenu

‎arch/powerpc/crypto/Makefile‎

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@@ -13,6 +13,7 @@ obj-$(CONFIG_CRYPTO_SHA256_PPC_SPE) += sha256-ppc-spe.o
1313
obj-$(CONFIG_CRYPTO_CRC32C_VPMSUM) += crc32c-vpmsum.o
1414
obj-$(CONFIG_CRYPTO_CRCT10DIF_VPMSUM) += crct10dif-vpmsum.o
1515
obj-$(CONFIG_CRYPTO_VPMSUM_TESTER) += crc-vpmsum_test.o
16+
obj-$(CONFIG_CRYPTO_AES_GCM_P10) += aes-gcm-p10-crypto.o
1617

1718
aes-ppc-spe-y := aes-spe-core.o aes-spe-keys.o aes-tab-4k.o aes-spe-modes.o aes-spe-glue.o
1819
md5-ppc-y := md5-asm.o md5-glue.o
@@ -21,3 +22,15 @@ sha1-ppc-spe-y := sha1-spe-asm.o sha1-spe-glue.o
2122
sha256-ppc-spe-y := sha256-spe-asm.o sha256-spe-glue.o
2223
crc32c-vpmsum-y := crc32c-vpmsum_asm.o crc32c-vpmsum_glue.o
2324
crct10dif-vpmsum-y := crct10dif-vpmsum_asm.o crct10dif-vpmsum_glue.o
25+
aes-gcm-p10-crypto-y := aes-gcm-p10-glue.o aes-gcm-p10.o ghashp8-ppc.o aesp8-ppc.o
26+
27+
quiet_cmd_perl = PERL $@
28+
cmd_perl = $(PERL) $< $(if $(CONFIG_CPU_LITTLE_ENDIAN), linux-ppc64le, linux-ppc64) > $@
29+
30+
targets += aesp8-ppc.S ghashp8-ppc.S
31+
32+
$(obj)/aesp8-ppc.S $(obj)/ghashp8-ppc.S: $(obj)/%.S: $(src)/%.pl FORCE
33+
$(call if_changed,perl)
34+
35+
OBJECT_FILES_NON_STANDARD_aesp8-ppc.o := y
36+
OBJECT_FILES_NON_STANDARD_ghashp8-ppc.o := y

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