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rmurphy-armwilldeacon
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iommu/arm-smmu-v3: Retire disable_bypass parameter
The disable_bypass parameter has been mostly meaningless for a long time since the introduction of default domains. Its original intent is now fulfilled by the controls users have over the default domain type, and its remaining effect in the brief window between Stream Table initialisation and default domain creation hardly seems worth the complication. Furthermore, thanks to 2-level Stream Tables, disabling disable_bypass (there's another reason not to like it right there) has never guaranteed that any particular StreamID *will* bypass anyway - any device which might actually care about that wants RMRs - so there's not really much lost by taking away that option (which has already been non-default for nearing 6 years now). As part of this, also remove the weird behaviour where we "successfully" probe and register a non-functional SMMU if the DT "#iommu-cells" property is wrong. I have no memory of what possessed me to think that was a good idea at the time, and by now I suspect it's likely to break things worse than simply failing probe would. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Mostafa Saleh <smostafa@google.com> Link: https://lore.kernel.org/r/ea3ac4cd595a81b5511729601b2f7d4668178438.1712335927.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
1 parent 39cd87c commit 734554f

1 file changed

Lines changed: 13 additions & 33 deletions

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drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

Lines changed: 13 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -30,11 +30,6 @@
3030
#include "arm-smmu-v3.h"
3131
#include "../../dma-iommu.h"
3232

33-
static bool disable_bypass = true;
34-
module_param(disable_bypass, bool, 0444);
35-
MODULE_PARM_DESC(disable_bypass,
36-
"Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
37-
3833
static bool disable_msipolling;
3934
module_param(disable_msipolling, bool, 0444);
4035
MODULE_PARM_DESC(disable_msipolling,
@@ -1567,17 +1562,13 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target,
15671562
* This can safely directly manipulate the STE memory without a sync sequence
15681563
* because the STE table has not been installed in the SMMU yet.
15691564
*/
1570-
static void arm_smmu_init_initial_stes(struct arm_smmu_device *smmu,
1571-
struct arm_smmu_ste *strtab,
1565+
static void arm_smmu_init_initial_stes(struct arm_smmu_ste *strtab,
15721566
unsigned int nent)
15731567
{
15741568
unsigned int i;
15751569

15761570
for (i = 0; i < nent; ++i) {
1577-
if (disable_bypass)
1578-
arm_smmu_make_abort_ste(strtab);
1579-
else
1580-
arm_smmu_make_bypass_ste(smmu, strtab);
1571+
arm_smmu_make_abort_ste(strtab);
15811572
strtab++;
15821573
}
15831574
}
@@ -1605,7 +1596,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
16051596
return -ENOMEM;
16061597
}
16071598

1608-
arm_smmu_init_initial_stes(smmu, desc->l2ptr, 1 << STRTAB_SPLIT);
1599+
arm_smmu_init_initial_stes(desc->l2ptr, 1 << STRTAB_SPLIT);
16091600
arm_smmu_write_strtab_l1_desc(strtab, desc);
16101601
return 0;
16111602
}
@@ -2915,10 +2906,10 @@ static void arm_smmu_release_device(struct device *dev)
29152906
iopf_queue_remove_device(master->smmu->evtq.iopf, dev);
29162907

29172908
/* Put the STE back to what arm_smmu_init_strtab() sets */
2918-
if (disable_bypass && !dev->iommu->require_direct)
2919-
arm_smmu_attach_dev_blocked(&arm_smmu_blocked_domain, dev);
2920-
else
2909+
if (dev->iommu->require_direct)
29212910
arm_smmu_attach_dev_identity(&arm_smmu_identity_domain, dev);
2911+
else
2912+
arm_smmu_attach_dev_blocked(&arm_smmu_blocked_domain, dev);
29222913

29232914
arm_smmu_disable_pasid(master);
29242915
arm_smmu_remove_master(master);
@@ -3273,7 +3264,7 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
32733264
reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);
32743265
cfg->strtab_base_cfg = reg;
32753266

3276-
arm_smmu_init_initial_stes(smmu, strtab, cfg->num_l1_ents);
3267+
arm_smmu_init_initial_stes(strtab, cfg->num_l1_ents);
32773268
return 0;
32783269
}
32793270

@@ -3503,7 +3494,7 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
35033494
return ret;
35043495
}
35053496

3506-
static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
3497+
static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
35073498
{
35083499
int ret;
35093500
u32 reg, enables;
@@ -3513,7 +3504,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
35133504
reg = readl_relaxed(smmu->base + ARM_SMMU_CR0);
35143505
if (reg & CR0_SMMUEN) {
35153506
dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n");
3516-
WARN_ON(is_kdump_kernel() && !disable_bypass);
35173507
arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0);
35183508
}
35193509

@@ -3620,14 +3610,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
36203610
if (is_kdump_kernel())
36213611
enables &= ~(CR0_EVTQEN | CR0_PRIQEN);
36223612

3623-
/* Enable the SMMU interface, or ensure bypass */
3624-
if (!bypass || disable_bypass) {
3625-
enables |= CR0_SMMUEN;
3626-
} else {
3627-
ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT);
3628-
if (ret)
3629-
return ret;
3630-
}
3613+
/* Enable the SMMU interface */
3614+
enables |= CR0_SMMUEN;
36313615
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
36323616
ARM_SMMU_CR0ACK);
36333617
if (ret) {
@@ -4019,7 +4003,6 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
40194003
resource_size_t ioaddr;
40204004
struct arm_smmu_device *smmu;
40214005
struct device *dev = &pdev->dev;
4022-
bool bypass;
40234006

40244007
smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
40254008
if (!smmu)
@@ -4030,12 +4013,9 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
40304013
ret = arm_smmu_device_dt_probe(pdev, smmu);
40314014
} else {
40324015
ret = arm_smmu_device_acpi_probe(pdev, smmu);
4033-
if (ret == -ENODEV)
4034-
return ret;
40354016
}
4036-
4037-
/* Set bypass mode according to firmware probing result */
4038-
bypass = !!ret;
4017+
if (ret)
4018+
return ret;
40394019

40404020
/* Base address */
40414021
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -4099,7 +4079,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
40994079
arm_smmu_rmr_install_bypass_ste(smmu);
41004080

41014081
/* Reset the device */
4102-
ret = arm_smmu_device_reset(smmu, bypass);
4082+
ret = arm_smmu_device_reset(smmu);
41034083
if (ret)
41044084
return ret;
41054085

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