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Merge tag 'mips_5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: "Cleanups and fixes" * tag 'mips_5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (38 commits) MIPS: RALINK: Define pci_remap_iospace under CONFIG_PCI_DRIVERS_GENERIC MIPS: Use memblock_add_node() in early_parse_mem() under CONFIG_NUMA MIPS: Return -EINVAL if mem parameter is empty in early_parse_mem() MIPS: Kconfig: Fix indentation and add endif comment MIPS: bmips: Fix compiler warning observed on W=1 build MIPS: Rewrite `csum_tcpudp_nofold' in plain C mips: setup: use strscpy to replace strlcpy MIPS: Octeon: add SNIC10E board MIPS: Ingenic: Refresh defconfig for CU1000-Neo and CU1830-Neo. MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards. MIPS: Ingenic: Add PWM nodes for X1830. MIPS: Octeon: fix typo in comment MIPS: loongson32: Kconfig: Remove extra space MIPS: Sibyte: remove unnecessary return variable MIPS: Use NOKPROBE_SYMBOL() instead of __kprobes annotation selftests/ftrace: Save kprobe_events to test log MIPS: tools: no need to initialise statics to 0 MIPS: Loongson: Use hwmon_device_register_with_groups() to register hwmon MIPS: VR41xx: Drop redundant spinlock initialization MIPS: smp: optimization for flush_tlb_mm when exiting ...
2 parents 2d2da47 + 7e4fd16 commit 73d15ba

62 files changed

Lines changed: 401 additions & 335 deletions

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‎arch/mips/Kconfig‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1321,11 +1321,11 @@ config CPU_LOONGSON64
13211321
select SWIOTLB
13221322
select HAVE_KVM
13231323
help
1324-
The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1325-
cores implements the MIPS64R2 instruction set with many extensions,
1326-
including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1327-
3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1328-
Loongson-2E/2F is not covered here and will be removed in future.
1324+
The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1325+
cores implements the MIPS64R2 instruction set with many extensions,
1326+
including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1327+
3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1328+
Loongson-2E/2F is not covered here and will be removed in future.
13291329

13301330
config LOONGSON3_ENHANCEMENT
13311331
bool "New Loongson-3 CPU Enhancements"
@@ -3255,7 +3255,7 @@ menu "CPU Power Management"
32553255

32563256
if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
32573257
source "drivers/cpufreq/Kconfig"
3258-
endif
3258+
endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
32593259

32603260
source "drivers/cpuidle/Kconfig"
32613261

‎arch/mips/alchemy/common/dbdma.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -574,7 +574,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
574574
dp++;
575575
}
576576

577-
/* Make last descrptor point to the first. */
577+
/* Make last descriptor point to the first. */
578578
dp--;
579579
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
580580
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;

‎arch/mips/bmips/dma.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
// SPDX-License-Identifier: GPL-2.0+
22

33
#include <linux/types.h>
4+
#include <linux/dma-map-ops.h>
45
#include <asm/bmips.h>
56
#include <asm/io.h>
67

‎arch/mips/boot/dts/brcm/bcm97358svmb.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@
7878
&qspi {
7979
status = "okay";
8080

81-
m25p80@0 {
81+
flash@0 {
8282
compatible = "m25p80";
8383
reg = <0>;
8484
spi-max-frequency = <40000000>;

‎arch/mips/boot/dts/brcm/bcm97360svmb.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@
8181
&qspi {
8282
status = "okay";
8383

84-
m25p80@0 {
84+
flash@0 {
8585
compatible = "m25p80";
8686
reg = <0>;
8787
spi-max-frequency = <40000000>;

‎arch/mips/boot/dts/brcm/bcm97425svmb.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@
116116
&qspi {
117117
status = "okay";
118118

119-
m25p80@0 {
119+
flash@0 {
120120
compatible = "m25p80";
121121
reg = <0>;
122122
spi-max-frequency = <40000000>;

‎arch/mips/boot/dts/ingenic/cu1000-neo.dts‎

Lines changed: 40 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -31,42 +31,6 @@
3131
};
3232
};
3333

34-
ssi: spi-gpio {
35-
compatible = "spi-gpio";
36-
#address-cells = <1>;
37-
#size-cells = <0>;
38-
num-chipselects = <1>;
39-
40-
mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
41-
miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
42-
sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
43-
cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
44-
45-
status = "okay";
46-
47-
spi-max-frequency = <50000000>;
48-
49-
sc16is752: expander@0 {
50-
compatible = "nxp,sc16is752";
51-
reg = <0>; /* CE0 */
52-
spi-max-frequency = <4000000>;
53-
54-
clocks = <&exclk_sc16is752>;
55-
56-
interrupt-parent = <&gpc>;
57-
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
58-
59-
gpio-controller;
60-
#gpio-cells = <2>;
61-
62-
exclk_sc16is752: sc16is752 {
63-
compatible = "fixed-clock";
64-
#clock-cells = <0>;
65-
clock-frequency = <48000000>;
66-
};
67-
};
68-
};
69-
7034
wlan_pwrseq: msc1-pwrseq {
7135
compatible = "mmc-pwrseq-simple";
7236

@@ -90,7 +54,7 @@
9054

9155
&ost {
9256
/* 1500 kHz for the system timer and clocksource */
93-
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
57+
assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
9458
assigned-clock-rates = <1500000>, <1500000>;
9559
};
9660

@@ -101,6 +65,39 @@
10165
pinctrl-0 = <&pins_uart2>;
10266
};
10367

68+
&ssi {
69+
status = "okay";
70+
71+
num-cs = <2>;
72+
cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
73+
74+
pinctrl-names = "default";
75+
pinctrl-0 = <&pins_ssi>;
76+
77+
sc16is752: expander@0 {
78+
compatible = "nxp,sc16is752";
79+
reg = <0>; /* CE0 */
80+
81+
spi-rx-bus-width = <1>;
82+
spi-tx-bus-width = <1>;
83+
spi-max-frequency = <4000000>;
84+
85+
clocks = <&exclk_sc16is752>;
86+
87+
interrupt-parent = <&gpc>;
88+
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
89+
90+
gpio-controller;
91+
#gpio-cells = <2>;
92+
93+
exclk_sc16is752: sc16is752 {
94+
compatible = "fixed-clock";
95+
#clock-cells = <0>;
96+
clock-frequency = <48000000>;
97+
};
98+
};
99+
};
100+
104101
&i2c0 {
105102
status = "okay";
106103

@@ -192,6 +189,12 @@
192189
bias-pull-up;
193190
};
194191

192+
pins_ssi: ssi {
193+
function = "ssi";
194+
groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
195+
bias-disable;
196+
};
197+
195198
pins_i2c0: i2c0 {
196199
function = "i2c0";
197200
groups = "i2c0-data";

‎arch/mips/boot/dts/ingenic/cu1830-neo.dts‎

Lines changed: 39 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -31,42 +31,6 @@
3131
};
3232
};
3333

34-
ssi0: spi-gpio {
35-
compatible = "spi-gpio";
36-
#address-cells = <1>;
37-
#size-cells = <0>;
38-
num-chipselects = <1>;
39-
40-
mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
41-
miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
42-
sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
43-
cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
44-
45-
status = "okay";
46-
47-
spi-max-frequency = <50000000>;
48-
49-
sc16is752: expander@0 {
50-
compatible = "nxp,sc16is752";
51-
reg = <0>; /* CE0 */
52-
spi-max-frequency = <4000000>;
53-
54-
clocks = <&exclk_sc16is752>;
55-
56-
interrupt-parent = <&gpb>;
57-
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
58-
59-
gpio-controller;
60-
#gpio-cells = <2>;
61-
62-
exclk_sc16is752: sc16is752 {
63-
compatible = "fixed-clock";
64-
#clock-cells = <0>;
65-
clock-frequency = <48000000>;
66-
};
67-
};
68-
};
69-
7034
wlan_pwrseq: msc1-pwrseq {
7135
compatible = "mmc-pwrseq-simple";
7236

@@ -90,7 +54,7 @@
9054

9155
&ost {
9256
/* 1500 kHz for the system timer and clocksource */
93-
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
57+
assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
9458
assigned-clock-rates = <1500000>, <1500000>;
9559
};
9660

@@ -101,6 +65,38 @@
10165
pinctrl-0 = <&pins_uart1>;
10266
};
10367

68+
&ssi0 {
69+
status = "okay";
70+
71+
num-cs = <2>;
72+
73+
pinctrl-names = "default";
74+
pinctrl-0 = <&pins_ssi0>;
75+
76+
sc16is752: expander@0 {
77+
compatible = "nxp,sc16is752";
78+
reg = <0>; /* CE0 */
79+
80+
spi-rx-bus-width = <1>;
81+
spi-tx-bus-width = <1>;
82+
spi-max-frequency = <4000000>;
83+
84+
clocks = <&exclk_sc16is752>;
85+
86+
interrupt-parent = <&gpb>;
87+
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
88+
89+
gpio-controller;
90+
#gpio-cells = <2>;
91+
92+
exclk_sc16is752: sc16is752 {
93+
compatible = "fixed-clock";
94+
#clock-cells = <0>;
95+
clock-frequency = <48000000>;
96+
};
97+
};
98+
};
99+
104100
&i2c0 {
105101
status = "okay";
106102

@@ -196,6 +192,12 @@
196192
bias-pull-up;
197193
};
198194

195+
pins_ssi0: ssi0 {
196+
function = "ssi0";
197+
groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
198+
bias-disable;
199+
};
200+
199201
pins_i2c0: i2c0 {
200202
function = "i2c0";
201203
groups = "i2c0-data";

‎arch/mips/boot/dts/ingenic/x1000.dtsi‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,18 @@
127127
clocks = <&tcu TCU_CLK_WDT>;
128128
clock-names = "wdt";
129129
};
130+
131+
pwm: pwm@40 {
132+
compatible = "ingenic,x1000-pwm";
133+
reg = <0x40 0x50>;
134+
135+
#pwm-cells = <3>;
136+
137+
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
138+
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
139+
<&tcu TCU_CLK_TIMER4>;
140+
clock-names = "timer0", "timer1", "timer2", "timer3", "timer4";
141+
};
130142
};
131143

132144
rtc: rtc@10003000 {
@@ -246,6 +258,25 @@
246258
status = "disabled";
247259
};
248260

261+
ssi: spi@10043000 {
262+
compatible = "ingenic,x1000-spi";
263+
reg = <0x10043000 0x20>;
264+
#address-cells = <1>;
265+
#size-cells = <0>;
266+
267+
interrupt-parent = <&intc>;
268+
interrupts = <8>;
269+
270+
clocks = <&cgu X1000_CLK_SSI>;
271+
clock-names = "spi";
272+
273+
dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
274+
<&pdma X1000_DMA_SSI0_TX 0xffffffff>;
275+
dma-names = "rx", "tx";
276+
277+
status = "disabled";
278+
};
279+
249280
i2c0: i2c-controller@10050000 {
250281
compatible = "ingenic,x1000-i2c";
251282
reg = <0x10050000 0x1000>;
@@ -291,6 +322,7 @@
291322
pdma: dma-controller@13420000 {
292323
compatible = "ingenic,x1000-dma";
293324
reg = <0x13420000 0x400>, <0x13421000 0x40>;
325+
294326
#dma-cells = <2>;
295327

296328
interrupt-parent = <&intc>;

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