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jason-jh.linChun-Kuang Hu
jason-jh.lin
authored and
Chun-Kuang Hu
committed
drm/mediatek: Adjust to the alphabetic order for mediatek-drm
Adjust to the alphabetic order for the define, function, struct and array in mediatek-drm driver Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
1 parent aa0c315 commit 73d3724

3 files changed

Lines changed: 131 additions & 134 deletions

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‎drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c‎

Lines changed: 59 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -20,42 +20,40 @@
2020
#include "mtk_drm_ddp_comp.h"
2121
#include "mtk_drm_crtc.h"
2222

23-
#define DISP_REG_OD_EN 0x0000
24-
#define DISP_REG_OD_CFG 0x0020
25-
#define DISP_REG_OD_SIZE 0x0030
26-
#define DISP_REG_DITHER_5 0x0114
27-
#define DISP_REG_DITHER_7 0x011c
28-
#define DISP_REG_DITHER_15 0x013c
29-
#define DISP_REG_DITHER_16 0x0140
30-
31-
#define DISP_REG_UFO_START 0x0000
3223

3324
#define DISP_REG_DITHER_EN 0x0000
3425
#define DITHER_EN BIT(0)
3526
#define DISP_REG_DITHER_CFG 0x0020
3627
#define DITHER_RELAY_MODE BIT(0)
3728
#define DITHER_ENGINE_EN BIT(1)
38-
#define DISP_REG_DITHER_SIZE 0x0030
39-
40-
#define OD_RELAYMODE BIT(0)
41-
42-
#define UFO_BYPASS BIT(2)
43-
4429
#define DISP_DITHERING BIT(2)
30+
#define DISP_REG_DITHER_SIZE 0x0030
31+
#define DISP_REG_DITHER_5 0x0114
32+
#define DISP_REG_DITHER_7 0x011c
33+
#define DISP_REG_DITHER_15 0x013c
4534
#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
4635
#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
4736
#define DITHER_NEW_BIT_MODE BIT(0)
37+
#define DISP_REG_DITHER_16 0x0140
4838
#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
4939
#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
5040
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
5141
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
5242

43+
#define DISP_REG_OD_EN 0x0000
44+
#define DISP_REG_OD_CFG 0x0020
45+
#define OD_RELAYMODE BIT(0)
46+
#define DISP_REG_OD_SIZE 0x0030
47+
5348
#define DISP_REG_POSTMASK_EN 0x0000
5449
#define POSTMASK_EN BIT(0)
5550
#define DISP_REG_POSTMASK_CFG 0x0020
5651
#define POSTMASK_RELAY_MODE BIT(0)
5752
#define DISP_REG_POSTMASK_SIZE 0x0030
5853

54+
#define DISP_REG_UFO_START 0x0000
55+
#define UFO_BYPASS BIT(2)
56+
5957
struct mtk_ddp_comp_dev {
6058
struct clk *clk;
6159
void __iomem *regs;
@@ -147,66 +145,58 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
147145
}
148146
}
149147

150-
static void mtk_dither_set(struct device *dev, unsigned int bpc,
151-
unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
152-
{
153-
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
154-
155-
mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
156-
DISP_DITHERING, cmdq_pkt);
157-
}
158-
159-
static void mtk_od_config(struct device *dev, unsigned int w,
160-
unsigned int h, unsigned int vrefresh,
161-
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
148+
static void mtk_dither_config(struct device *dev, unsigned int w,
149+
unsigned int h, unsigned int vrefresh,
150+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
162151
{
163152
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
164153

165-
mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
166-
mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
167-
mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
154+
mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
155+
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
156+
DISP_REG_DITHER_CFG);
157+
mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
158+
DITHER_ENGINE_EN, cmdq_pkt);
168159
}
169160

170-
static void mtk_od_start(struct device *dev)
161+
static void mtk_dither_start(struct device *dev)
171162
{
172163
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
173164

174-
writel(1, priv->regs + DISP_REG_OD_EN);
165+
writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
175166
}
176167

177-
static void mtk_ufoe_start(struct device *dev)
168+
static void mtk_dither_stop(struct device *dev)
178169
{
179170
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
180171

181-
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
172+
writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
182173
}
183174

184-
static void mtk_dither_config(struct device *dev, unsigned int w,
185-
unsigned int h, unsigned int vrefresh,
186-
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
175+
static void mtk_dither_set(struct device *dev, unsigned int bpc,
176+
unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
187177
{
188178
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
189179

190-
mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
191-
DISP_REG_DITHER_SIZE);
192-
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
193-
DISP_REG_DITHER_CFG);
194-
mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
195-
DITHER_ENGINE_EN, cmdq_pkt);
180+
mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
181+
DISP_DITHERING, cmdq_pkt);
196182
}
197183

198-
static void mtk_dither_start(struct device *dev)
184+
static void mtk_od_config(struct device *dev, unsigned int w,
185+
unsigned int h, unsigned int vrefresh,
186+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
199187
{
200188
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
201189

202-
writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
190+
mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
191+
mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
192+
mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
203193
}
204194

205-
static void mtk_dither_stop(struct device *dev)
195+
static void mtk_od_start(struct device *dev)
206196
{
207197
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
208198

209-
writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
199+
writel(1, priv->regs + DISP_REG_OD_EN);
210200
}
211201

212202
static void mtk_postmask_config(struct device *dev, unsigned int w,
@@ -235,6 +225,13 @@ static void mtk_postmask_stop(struct device *dev)
235225
writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
236226
}
237227

228+
static void mtk_ufoe_start(struct device *dev)
229+
{
230+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
231+
232+
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
233+
}
234+
238235
static const struct mtk_ddp_comp_funcs ddp_aal = {
239236
.clk_enable = mtk_aal_clk_enable,
240237
.clk_disable = mtk_aal_clk_disable,
@@ -337,23 +334,23 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
337334
};
338335

339336
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
340-
[MTK_DISP_OVL] = "ovl",
341-
[MTK_DISP_OVL_2L] = "ovl-2l",
342-
[MTK_DISP_RDMA] = "rdma",
343-
[MTK_DISP_WDMA] = "wdma",
344-
[MTK_DISP_COLOR] = "color",
345-
[MTK_DISP_CCORR] = "ccorr",
346337
[MTK_DISP_AAL] = "aal",
347-
[MTK_DISP_GAMMA] = "gamma",
338+
[MTK_DISP_BLS] = "bls",
339+
[MTK_DISP_CCORR] = "ccorr",
340+
[MTK_DISP_COLOR] = "color",
348341
[MTK_DISP_DITHER] = "dither",
349-
[MTK_DISP_UFOE] = "ufoe",
350-
[MTK_DSI] = "dsi",
351-
[MTK_DPI] = "dpi",
352-
[MTK_DISP_PWM] = "pwm",
342+
[MTK_DISP_GAMMA] = "gamma",
353343
[MTK_DISP_MUTEX] = "mutex",
354344
[MTK_DISP_OD] = "od",
355-
[MTK_DISP_BLS] = "bls",
345+
[MTK_DISP_OVL] = "ovl",
346+
[MTK_DISP_OVL_2L] = "ovl-2l",
356347
[MTK_DISP_POSTMASK] = "postmask",
348+
[MTK_DISP_PWM] = "pwm",
349+
[MTK_DISP_RDMA] = "rdma",
350+
[MTK_DISP_UFOE] = "ufoe",
351+
[MTK_DISP_WDMA] = "wdma",
352+
[MTK_DPI] = "dpi",
353+
[MTK_DSI] = "dsi",
357354
};
358355

359356
struct mtk_ddp_comp_match {
@@ -511,12 +508,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
511508
type == MTK_DISP_CCORR ||
512509
type == MTK_DISP_COLOR ||
513510
type == MTK_DISP_GAMMA ||
514-
type == MTK_DPI ||
515-
type == MTK_DSI ||
516511
type == MTK_DISP_OVL ||
517512
type == MTK_DISP_OVL_2L ||
518513
type == MTK_DISP_PWM ||
519-
type == MTK_DISP_RDMA)
514+
type == MTK_DISP_RDMA ||
515+
type == MTK_DPI ||
516+
type == MTK_DSI)
520517
return 0;
521518

522519
priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);

‎drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -18,23 +18,23 @@ struct mtk_plane_state;
1818
struct drm_crtc_state;
1919

2020
enum mtk_ddp_comp_type {
21-
MTK_DISP_OVL,
22-
MTK_DISP_OVL_2L,
23-
MTK_DISP_RDMA,
24-
MTK_DISP_WDMA,
25-
MTK_DISP_COLOR,
21+
MTK_DISP_AAL,
22+
MTK_DISP_BLS,
2623
MTK_DISP_CCORR,
24+
MTK_DISP_COLOR,
2725
MTK_DISP_DITHER,
28-
MTK_DISP_AAL,
2926
MTK_DISP_GAMMA,
30-
MTK_DISP_UFOE,
31-
MTK_DSI,
32-
MTK_DPI,
33-
MTK_DISP_POSTMASK,
34-
MTK_DISP_PWM,
3527
MTK_DISP_MUTEX,
3628
MTK_DISP_OD,
37-
MTK_DISP_BLS,
29+
MTK_DISP_OVL,
30+
MTK_DISP_OVL_2L,
31+
MTK_DISP_POSTMASK,
32+
MTK_DISP_PWM,
33+
MTK_DISP_RDMA,
34+
MTK_DISP_UFOE,
35+
MTK_DISP_WDMA,
36+
MTK_DPI,
37+
MTK_DSI,
3838
MTK_DDP_COMP_TYPE_MAX,
3939
};
4040

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