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Phil Edworthygeertu
Phil Edworthy
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geertu
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clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
All of the muxes and dividers that can be modified require the HIWORD flags, so make the macros set them. It won't affect read only muxes and dividers. This will make the clock tables a little easier to read, particularly for new SoCs coming. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-8-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 8282fe0 commit 75b0ad4

3 files changed

Lines changed: 19 additions & 31 deletions

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‎drivers/clk/renesas/r9a07g043-cpg.c‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -99,30 +99,24 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
9999
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
100100
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
101101
DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
102-
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
103-
DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
102+
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
104103
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
105104
DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
106105
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
107106
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
108107
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
109108

110109
/* Core output clk */
111-
DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
112-
CLK_DIVIDER_HIWORD_MASK),
113-
DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
114-
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
110+
DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
111+
DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
115112
DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
116113
DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
117-
DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
118-
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
114+
DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
119115
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
120-
DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2,
121-
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
116+
DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
122117
DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
123118
DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
124-
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2,
125-
sel_pll6_2, 0, CLK_MUX_HIWORD_MASK),
119+
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
126120
DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
127121
DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
128122
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),

‎drivers/clk/renesas/r9a07g044-cpg.c‎

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -139,8 +139,7 @@ static const struct {
139139
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
140140
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
141141
DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
142-
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
143-
DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
142+
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
144143

145144
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
146145
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -149,32 +148,26 @@ static const struct {
149148
DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
150149
DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
151150
DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
152-
DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK),
151+
DIVDSILPCLK, dtable_16_128),
153152

154153
/* Core output clk */
155-
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
156-
CLK_DIVIDER_HIWORD_MASK),
157-
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
158-
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
154+
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
155+
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
159156
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
160157
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
161-
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
162-
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
158+
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
163159
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
164-
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
165-
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
160+
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
166161
DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
167162
DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
168-
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
169-
sel_pll6_2, 0, CLK_MUX_HIWORD_MASK),
163+
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
170164
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
171165
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
172166
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
173167
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
174168
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
175169
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
176-
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
177-
CLK_DIVIDER_HIWORD_MASK),
170+
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
178171
DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
179172
DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
180173
DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),

‎drivers/clk/renesas/rzg2l-cpg.h‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,18 +135,19 @@ enum clk_types {
135135
DEF_TYPE(_name, _id, CLK_TYPE_IN)
136136
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
137137
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
138-
#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
138+
#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
139139
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
140-
.parent = _parent, .dtable = _dtable, .flag = _flag)
140+
.parent = _parent, .dtable = _dtable, \
141+
.flag = CLK_DIVIDER_HIWORD_MASK)
141142
#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
142143
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
143144
.parent = _parent, .dtable = _dtable, \
144145
.flag = CLK_DIVIDER_READ_ONLY)
145-
#define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \
146+
#define DEF_MUX(_name, _id, _conf, _parent_names) \
146147
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
147148
.parent_names = _parent_names, \
148149
.num_parents = ARRAY_SIZE(_parent_names), \
149-
.flag = _flag, .mux_flags = _mux_flags)
150+
.mux_flags = CLK_MUX_HIWORD_MASK)
150151
#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
151152
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
152153
.parent_names = _parent_names, \

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