@@ -910,6 +910,98 @@ static const struct mdp5_cfg_hw msm8998_config = {
910910 .max_clk = 412500000 ,
911911};
912912
913+ static const struct mdp5_cfg_hw sdm630_config = {
914+ .name = "sdm630" ,
915+ .mdp = {
916+ .count = 1 ,
917+ .caps = MDP_CAP_CDM |
918+ MDP_CAP_SRC_SPLIT |
919+ 0 ,
920+ },
921+ .ctl = {
922+ .count = 5 ,
923+ .base = { 0x01000 , 0x01200 , 0x01400 , 0x01600 , 0x01800 },
924+ .flush_hw_mask = 0xf4ffffff ,
925+ },
926+ .pipe_vig = {
927+ .count = 1 ,
928+ .base = { 0x04000 },
929+ .caps = MDP_PIPE_CAP_HFLIP |
930+ MDP_PIPE_CAP_VFLIP |
931+ MDP_PIPE_CAP_SCALE |
932+ MDP_PIPE_CAP_CSC |
933+ MDP_PIPE_CAP_DECIMATION |
934+ MDP_PIPE_CAP_SW_PIX_EXT |
935+ 0 ,
936+ },
937+ .pipe_rgb = {
938+ .count = 4 ,
939+ .base = { 0x14000 , 0x16000 , 0x18000 , 0x1a000 },
940+ .caps = MDP_PIPE_CAP_HFLIP |
941+ MDP_PIPE_CAP_VFLIP |
942+ MDP_PIPE_CAP_SCALE |
943+ MDP_PIPE_CAP_DECIMATION |
944+ MDP_PIPE_CAP_SW_PIX_EXT |
945+ 0 ,
946+ },
947+ .pipe_dma = {
948+ .count = 2 , /* driver supports max of 2 currently */
949+ .base = { 0x24000 , 0x26000 , 0x28000 },
950+ .caps = MDP_PIPE_CAP_HFLIP |
951+ MDP_PIPE_CAP_VFLIP |
952+ MDP_PIPE_CAP_SW_PIX_EXT |
953+ 0 ,
954+ },
955+ .pipe_cursor = {
956+ .count = 1 ,
957+ .base = { 0x34000 },
958+ .caps = MDP_PIPE_CAP_HFLIP |
959+ MDP_PIPE_CAP_VFLIP |
960+ MDP_PIPE_CAP_SW_PIX_EXT |
961+ MDP_PIPE_CAP_CURSOR |
962+ 0 ,
963+ },
964+
965+ .lm = {
966+ .count = 2 ,
967+ .base = { 0x44000 , 0x46000 },
968+ .instances = {
969+ { .id = 0 , .pp = 0 , .dspp = 0 ,
970+ .caps = MDP_LM_CAP_DISPLAY |
971+ MDP_LM_CAP_PAIR , },
972+ { .id = 1 , .pp = 1 , .dspp = -1 ,
973+ .caps = MDP_LM_CAP_WB , },
974+ },
975+ .nb_stages = 8 ,
976+ .max_width = 2048 ,
977+ .max_height = 0xFFFF ,
978+ },
979+ .dspp = {
980+ .count = 1 ,
981+ .base = { 0x54000 },
982+ },
983+ .ad = {
984+ .count = 2 ,
985+ .base = { 0x78000 , 0x78800 },
986+ },
987+ .pp = {
988+ .count = 3 ,
989+ .base = { 0x70000 , 0x71000 , 0x72000 },
990+ },
991+ .cdm = {
992+ .count = 1 ,
993+ .base = { 0x79200 },
994+ },
995+ .intf = {
996+ .base = { 0x6a000 , 0x6a800 },
997+ .connect = {
998+ [0 ] = INTF_DISABLED ,
999+ [1 ] = INTF_DSI ,
1000+ },
1001+ },
1002+ .max_clk = 412500000 ,
1003+ };
1004+
9131005static const struct mdp5_cfg_handler cfg_handlers_v1 [] = {
9141006 { .revision = 0 , .config = { .hw = & msm8x74v1_config } },
9151007 { .revision = 2 , .config = { .hw = & msm8x74v2_config } },
@@ -924,6 +1016,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
9241016
9251017static const struct mdp5_cfg_handler cfg_handlers_v3 [] = {
9261018 { .revision = 0 , .config = { .hw = & msm8998_config } },
1019+ { .revision = 3 , .config = { .hw = & sdm630_config } },
9271020};
9281021
9291022static struct mdp5_cfg_platform * mdp5_get_config (struct platform_device * dev );
0 commit comments