|
34 | 34 | * Special configuration registers directly in the first few words |
35 | 35 | * in I/O space. |
36 | 36 | */ |
37 | | -#define PCI_IOSIZE 0x00 |
38 | | -#define PCI_PROT 0x04 /* AHB protection */ |
39 | | -#define PCI_CTRL 0x08 /* PCI control signal */ |
40 | | -#define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */ |
41 | | -#define PCI_CONFIG 0x28 /* PCI configuration command register */ |
42 | | -#define PCI_DATA 0x2C |
| 37 | +#define FTPCI_IOSIZE 0x00 |
| 38 | +#define FTPCI_PROT 0x04 /* AHB protection */ |
| 39 | +#define FTPCI_CTRL 0x08 /* PCI control signal */ |
| 40 | +#define FTPCI_SOFTRST 0x10 /* Soft reset counter and response error enable */ |
| 41 | +#define FTPCI_CONFIG 0x28 /* PCI configuration command register */ |
| 42 | +#define FTPCI_DATA 0x2C |
43 | 43 |
|
44 | 44 | #define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */ |
45 | 45 | #define FARADAY_PCI_PMC 0x40 /* Power management control */ |
@@ -195,9 +195,9 @@ static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number, |
195 | 195 | PCI_CONF_FUNCTION(PCI_FUNC(fn)) | |
196 | 196 | PCI_CONF_WHERE(config) | |
197 | 197 | PCI_CONF_ENABLE, |
198 | | - p->base + PCI_CONFIG); |
| 198 | + p->base + FTPCI_CONFIG); |
199 | 199 |
|
200 | | - *value = readl(p->base + PCI_DATA); |
| 200 | + *value = readl(p->base + FTPCI_DATA); |
201 | 201 |
|
202 | 202 | if (size == 1) |
203 | 203 | *value = (*value >> (8 * (config & 3))) & 0xFF; |
@@ -230,17 +230,17 @@ static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number, |
230 | 230 | PCI_CONF_FUNCTION(PCI_FUNC(fn)) | |
231 | 231 | PCI_CONF_WHERE(config) | |
232 | 232 | PCI_CONF_ENABLE, |
233 | | - p->base + PCI_CONFIG); |
| 233 | + p->base + FTPCI_CONFIG); |
234 | 234 |
|
235 | 235 | switch (size) { |
236 | 236 | case 4: |
237 | | - writel(value, p->base + PCI_DATA); |
| 237 | + writel(value, p->base + FTPCI_DATA); |
238 | 238 | break; |
239 | 239 | case 2: |
240 | | - writew(value, p->base + PCI_DATA + (config & 3)); |
| 240 | + writew(value, p->base + FTPCI_DATA + (config & 3)); |
241 | 241 | break; |
242 | 242 | case 1: |
243 | | - writeb(value, p->base + PCI_DATA + (config & 3)); |
| 243 | + writeb(value, p->base + FTPCI_DATA + (config & 3)); |
244 | 244 | break; |
245 | 245 | default: |
246 | 246 | ret = PCIBIOS_BAD_REGISTER_NUMBER; |
@@ -469,19 +469,19 @@ static int faraday_pci_probe(struct platform_device *pdev) |
469 | 469 | if (!faraday_res_to_memcfg(io->start - win->offset, |
470 | 470 | resource_size(io), &val)) { |
471 | 471 | /* setup I/O space size */ |
472 | | - writel(val, p->base + PCI_IOSIZE); |
| 472 | + writel(val, p->base + FTPCI_IOSIZE); |
473 | 473 | } else { |
474 | 474 | dev_err(dev, "illegal IO mem size\n"); |
475 | 475 | return -EINVAL; |
476 | 476 | } |
477 | 477 | } |
478 | 478 |
|
479 | 479 | /* Setup hostbridge */ |
480 | | - val = readl(p->base + PCI_CTRL); |
| 480 | + val = readl(p->base + FTPCI_CTRL); |
481 | 481 | val |= PCI_COMMAND_IO; |
482 | 482 | val |= PCI_COMMAND_MEMORY; |
483 | 483 | val |= PCI_COMMAND_MASTER; |
484 | | - writel(val, p->base + PCI_CTRL); |
| 484 | + writel(val, p->base + FTPCI_CTRL); |
485 | 485 | /* Mask and clear all interrupts */ |
486 | 486 | faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000); |
487 | 487 | if (variant->cascaded_irq) { |
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