Skip to content

Commit 77fe8f1

Browse files
airliedairlied
committed
Merge tag 'amd-drm-fixes-6.8-2024-01-25' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.8-2024-01-25: amdgpu: - AC/DC power supply tracking fix - Don't show invalid vram vendor data - SMU 13.0.x fixes - GART fix for umr on systems without VRAM - GFX 10/11 UNORD_DISPATCH fixes - IPS display fixes (required for S0ix on some platforms) - Misc fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240125221503.5019-1-alexander.deucher@amd.com
2 parents 83cd3be + c82eb25 commit 77fe8f1

24 files changed

Lines changed: 229 additions & 36 deletions

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,7 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
121121
struct amdgpu_bo_param bp;
122122
dma_addr_t dma_addr;
123123
struct page *p;
124+
unsigned long x;
124125
int ret;
125126

126127
if (adev->gart.bo != NULL)
@@ -130,6 +131,10 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
130131
if (!p)
131132
return -ENOMEM;
132133

134+
/* assign pages to this device */
135+
for (x = 0; x < (1UL << order); x++)
136+
p[x].mapping = adev->mman.bdev.dev_mapping;
137+
133138
/* If the hardware does not support UTCL2 snooping of the CPU caches
134139
* then set_memory_wc() could be used as a workaround to mark the pages
135140
* as write combine memory.
@@ -223,6 +228,7 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
223228
unsigned int order = get_order(adev->gart.table_size);
224229
struct sg_table *sg = adev->gart.bo->tbo.sg;
225230
struct page *p;
231+
unsigned long x;
226232
int ret;
227233

228234
ret = amdgpu_bo_reserve(adev->gart.bo, false);
@@ -234,6 +240,8 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
234240
sg_free_table(sg);
235241
kfree(sg);
236242
p = virt_to_page(adev->gart.ptr);
243+
for (x = 0; x < (1UL << order); x++)
244+
p[x].mapping = NULL;
237245
__free_pages(p, order);
238246

239247
adev->gart.ptr = NULL;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,8 +221,23 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = {
221221
NULL
222222
};
223223

224+
static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj,
225+
struct attribute *attr, int i)
226+
{
227+
struct device *dev = kobj_to_dev(kobj);
228+
struct drm_device *ddev = dev_get_drvdata(dev);
229+
struct amdgpu_device *adev = drm_to_adev(ddev);
230+
231+
if (attr == &dev_attr_mem_info_vram_vendor.attr &&
232+
!adev->gmc.vram_vendor)
233+
return 0;
234+
235+
return attr->mode;
236+
}
237+
224238
const struct attribute_group amdgpu_vram_mgr_attr_group = {
225-
.attrs = amdgpu_vram_mgr_attributes
239+
.attrs = amdgpu_vram_mgr_attributes,
240+
.is_visible = amdgpu_vram_attrs_is_visible
226241
};
227242

228243
/**

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6589,7 +6589,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
65896589
#ifdef __BIG_ENDIAN
65906590
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
65916591
#endif
6592-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6592+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
65936593
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
65946594
prop->allow_tunneling);
65956595
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3846,7 +3846,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
38463846
(order_base_2(prop->queue_size / 4) - 1));
38473847
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
38483848
(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3849-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3849+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
38503850
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
38513851
prop->allow_tunneling);
38523852
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

‎drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1950,7 +1950,8 @@ static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
19501950
static const u32 regBIF_BIOS_SCRATCH_4 = 0x50;
19511951
u32 vram_info;
19521952

1953-
if (!amdgpu_sriov_vf(adev)) {
1953+
/* Only for dGPU, vendor informaton is reliable */
1954+
if (!amdgpu_sriov_vf(adev) && !(adev->flags & AMD_IS_APU)) {
19541955
vram_info = RREG32(regBIF_BIOS_SCRATCH_4);
19551956
adev->gmc.vram_vendor = vram_info & 0xF;
19561957
}

‎drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
170170
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
171171
m->cp_hqd_pq_control |=
172172
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
173+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
173174
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
174175

175176
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

‎drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -224,6 +224,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
224224
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
225225
m->cp_hqd_pq_control |=
226226
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
227+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
227228
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
228229

229230
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -272,6 +272,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
272272
{
273273
u32 v_blank_start, v_blank_end, h_position, v_position;
274274
struct amdgpu_crtc *acrtc = NULL;
275+
struct dc *dc = adev->dm.dc;
275276

276277
if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
277278
return -EINVAL;
@@ -284,6 +285,9 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
284285
return 0;
285286
}
286287

288+
if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
289+
dc_allow_idle_optimizations(dc, false);
290+
287291
/*
288292
* TODO rework base driver to use values directly.
289293
* for now parse it back into reg-format
@@ -1715,7 +1719,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
17151719
init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
17161720
init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
17171721

1718-
init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1722+
if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
1723+
init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1724+
1725+
init_data.flags.disable_ips_in_vpb = 1;
17191726

17201727
/* Enable DWB for tested platforms only */
17211728
if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
@@ -8976,16 +8983,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
89768983

89778984
trace_amdgpu_dm_atomic_commit_tail_begin(state);
89788985

8979-
if (dm->dc->caps.ips_support) {
8980-
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8981-
if (new_con_state->crtc &&
8982-
new_con_state->crtc->state->active &&
8983-
drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8984-
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
8985-
break;
8986-
}
8987-
}
8988-
}
8986+
if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed)
8987+
dc_allow_idle_optimizations(dm->dc, false);
89898988

89908989
drm_atomic_helper_update_legacy_modeset_state(dev, state);
89918990
drm_dp_mst_atomic_wait_for_dependencies(state);

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
711711
{
712712
bool st;
713713
enum dc_irq_source irq_source;
714-
714+
struct dc *dc = adev->dm.dc;
715715
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
716716

717717
if (!acrtc) {
@@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
729729

730730
st = (state == AMDGPU_IRQ_STATE_ENABLE);
731731

732+
if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
733+
dc_allow_idle_optimizations(dc, false);
734+
732735
dc_interrupt_set(adev->dm.dc, irq_source, st);
733736
return 0;
734737
}

‎drivers/gpu/drm/amd/display/dc/dc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -434,6 +434,7 @@ struct dc_config {
434434
bool EnableMinDispClkODM;
435435
bool enable_auto_dpm_test_logs;
436436
unsigned int disable_ips;
437+
unsigned int disable_ips_in_vpb;
437438
};
438439

439440
enum visual_confirm {

0 commit comments

Comments
 (0)