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phy: rockchip: inno-dsidphy: Add support for rk3506
For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106020632.92-7-kernel@airkyi.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 file changed

Lines changed: 88 additions & 3 deletions

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‎drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c‎

Lines changed: 88 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -99,10 +99,30 @@
9999
#define VOD_MID_RANGE 0x3
100100
#define VOD_BIG_RANGE 0x7
101101
#define VOD_MAX_RANGE 0xf
102+
/* Analog Register Part: reg18 */
103+
#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6)
104+
#define LANE0_PRE_EMPHASIS_ENABLE BIT(6)
105+
#define LANE0_PRE_EMPHASIS_DISABLE 0
106+
#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5)
107+
#define LANE1_PRE_EMPHASIS_ENABLE BIT(5)
108+
#define LANE1_PRE_EMPHASIS_DISABLE 0
109+
/* Analog Register Part: reg19 */
110+
#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
111+
#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
102112
/* Analog Register Part: reg1E */
103113
#define PLL_MODE_SEL_MASK GENMASK(6, 5)
104114
#define PLL_MODE_SEL_LVDS_MODE 0
105115
#define PLL_MODE_SEL_MIPI_MODE BIT(5)
116+
/* Analog Register Part: reg20 */
117+
#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
118+
#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
119+
/* Analog Register Part: reg21 */
120+
#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
121+
#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
122+
#define PRE_EMPHASIS_MIN_RANGE 0x0
123+
#define PRE_EMPHASIS_MID_RANGE 0x1
124+
#define PRE_EMPHASIS_MAX_RANGE 0x2
125+
#define PRE_EMPHASIS_RESERVED_RANGE 0x3
106126
/* Digital Register Part: reg00 */
107127
#define REG_DIG_RSTN_MASK BIT(0)
108128
#define REG_DIG_RSTN_NORMAL BIT(0)
@@ -193,13 +213,15 @@
193213

194214
enum phy_max_rate {
195215
MAX_1GHZ,
216+
MAX_1_5GHZ,
196217
MAX_2_5GHZ,
197218
};
198219

199220
struct inno_video_phy_plat_data {
200221
const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
201222
const unsigned int num_timings;
202223
enum phy_max_rate max_rate;
224+
unsigned int max_lanes;
203225
};
204226

205227
struct inno_dsidphy {
@@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = {
258280
{1000000000, 0x0, 0x09, 0x20, 0x09, 0x27},
259281
};
260282

283+
static const
284+
struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = {
285+
{ 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
286+
{ 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
287+
{ 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
288+
{ 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
289+
{ 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
290+
{ 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
291+
{ 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
292+
{ 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
293+
{ 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
294+
{ 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
295+
{1000, 0x05, 0x08, 0x20, 0x09, 0x30},
296+
{1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
297+
{1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
298+
{1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
299+
};
300+
261301
static const
262302
struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = {
263303
{ 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02},
@@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
372412
u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
373413
u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
374414
unsigned int i;
415+
u32 val;
375416

376417
timings = inno->pdata->inno_mipi_dphy_timing_table;
377418

@@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
393434
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
394435
CLOCK_LANE_VOD_RANGE_SET_MASK,
395436
CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
437+
} else if (inno->pdata->max_rate == MAX_1_5GHZ) {
438+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
439+
LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE);
440+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
441+
LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE);
442+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19,
443+
PRE_EMPHASIS_RANGE_SET_MASK,
444+
PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
445+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a,
446+
LANE0_PRE_EMPHASIS_RANGE_SET_MASK,
447+
LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
448+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b,
449+
LANE1_PRE_EMPHASIS_RANGE_SET_MASK,
450+
LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
451+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
452+
CLOCK_LANE_VOD_RANGE_SET_MASK,
453+
CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
396454
}
397455
/* Enable PLL and LDO */
398456
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
@@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
518576
T_TA_WAIT_CNT(ta_wait));
519577
}
520578

521-
/* Enable all lanes on analog part */
579+
/* Enable lanes on analog part */
580+
switch (inno->pdata->max_lanes) {
581+
case 1:
582+
val = LANE_EN_0;
583+
break;
584+
case 2:
585+
val = LANE_EN_0 | LANE_EN_1;
586+
break;
587+
case 3:
588+
val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2;
589+
break;
590+
case 4:
591+
default:
592+
val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3;
593+
break;
594+
}
595+
522596
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
523-
LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
524-
LANE_EN_1 | LANE_EN_0);
597+
LANE_EN_MASK, LANE_EN_CK | val);
525598
}
526599

527600
static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
@@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = {
680753
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz,
681754
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz),
682755
.max_rate = MAX_1GHZ,
756+
.max_lanes = 4,
757+
};
758+
759+
static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = {
760+
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz,
761+
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz),
762+
.max_rate = MAX_1_5GHZ,
763+
.max_lanes = 2,
683764
};
684765

685766
static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = {
686767
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz,
687768
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz),
688769
.max_rate = MAX_2_5GHZ,
770+
.max_lanes = 4,
689771
};
690772

691773
static int inno_dsidphy_probe(struct platform_device *pdev)
@@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = {
767849
}, {
768850
.compatible = "rockchip,rk3368-dsi-dphy",
769851
.data = &max_1ghz_video_phy_plat_data,
852+
}, {
853+
.compatible = "rockchip,rk3506-dsi-dphy",
854+
.data = &max_1_5ghz_video_phy_plat_data,
770855
}, {
771856
.compatible = "rockchip,rk3568-dsi-dphy",
772857
.data = &max_2_5ghz_video_phy_plat_data,

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