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Merge tag 'riscv-for-linus-5.17-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt: - Support for sv48 paging - Hart ID mappings are now sparse, which enables more CPUs to come up on systems with sparse hart IDs - A handful of cleanups and fixes * tag 'riscv-for-linus-5.17-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (27 commits) RISC-V: nommu_virt: Drop unused SLAB_MERGE_DEFAULT RISC-V: Remove redundant err variable riscv: dts: sifive unmatched: Add gpio poweroff riscv: canaan: remove useless select of non-existing config SYSCON RISC-V: Do not use cpumask data structure for hartid bitmap RISC-V: Move spinwait booting method to its own config RISC-V: Move the entire hart selection via lottery to SMP RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method RISC-V: Do not print the SBI version during HSM extension boot print RISC-V: Avoid using per cpu array for ordered booting riscv: default to CONFIG_RISCV_SBI_V01=n riscv: fix boolconv.cocci warnings riscv: Explicit comment about user virtual address space size riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo riscv: Implement sv48 support asm-generic: Prepare for riscv use of pud_alloc_one and pud_free riscv: Allow to dynamically define VA_BITS riscv: Introduce functions to switch pt_ops riscv: Split early kasan mapping to prepare sv48 introduction riscv: Move KASAN mapping next to the kernel mapping ...
2 parents b21bae9 + c59cd50 commit 7867e40

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Lines changed: 1006 additions & 425 deletions

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‎Documentation/riscv/vm-layout.rst‎

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@@ -47,12 +47,12 @@ RISC-V Linux Kernel SV39
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| Kernel-space virtual memory, shared between all processes:
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____________________________________________________________|___________________________________________________________
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| | | |
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ffffffc000000000 | -256 GB | ffffffc7ffffffff | 32 GB | kasan
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ffffffcefee00000 | -196 GB | ffffffcefeffffff | 2 MB | fixmap
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ffffffceff000000 | -196 GB | ffffffceffffffff | 16 MB | PCI io
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ffffffcf00000000 | -196 GB | ffffffcfffffffff | 4 GB | vmemmap
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ffffffd000000000 | -192 GB | ffffffdfffffffff | 64 GB | vmalloc/ioremap space
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ffffffe000000000 | -128 GB | ffffffff7fffffff | 124 GB | direct mapping of all physical memory
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ffffffc6fee00000 | -228 GB | ffffffc6feffffff | 2 MB | fixmap
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ffffffc6ff000000 | -228 GB | ffffffc6ffffffff | 16 MB | PCI io
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ffffffc700000000 | -228 GB | ffffffc7ffffffff | 4 GB | vmemmap
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ffffffc800000000 | -224 GB | ffffffd7ffffffff | 64 GB | vmalloc/ioremap space
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ffffffd800000000 | -160 GB | fffffff6ffffffff | 124 GB | direct mapping of all physical memory
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fffffff700000000 | -36 GB | fffffffeffffffff | 32 GB | kasan
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__________________|____________|__________________|_________|____________________________________________________________
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|
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|

‎arch/riscv/Kconfig‎

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@@ -147,27 +147,16 @@ config MMU
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Select if you want MMU-based virtualised addressing space
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support by paged memory management. If unsure, say 'Y'.
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config VA_BITS
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int
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default 32 if 32BIT
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default 39 if 64BIT
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config PA_BITS
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int
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default 34 if 32BIT
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default 56 if 64BIT
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config PAGE_OFFSET
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hex
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default 0xC0000000 if 32BIT && MAXPHYSMEM_1GB
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default 0xC0000000 if 32BIT
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default 0x80000000 if 64BIT && !MMU
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default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB
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default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB
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default 0xffffaf8000000000 if 64BIT
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config KASAN_SHADOW_OFFSET
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hex
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depends on KASAN_GENERIC
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default 0xdfffffc800000000 if 64BIT
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default 0xdfffffff00000000 if 64BIT
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default 0xffffffff if 32BIT
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config ARCH_FLATMEM_ENABLE
@@ -213,7 +202,7 @@ config FIX_EARLYCON_MEM
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config PGTABLE_LEVELS
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int
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default 3 if 64BIT
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default 4 if 64BIT
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default 2
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config LOCKDEP_SUPPORT
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bool
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select HAVE_MOD_ARCH_SPECIFIC
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choice
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prompt "Maximum Physical Memory"
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default MAXPHYSMEM_1GB if 32BIT
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default MAXPHYSMEM_2GB if 64BIT && CMODEL_MEDLOW
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default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
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config MAXPHYSMEM_1GB
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depends on 32BIT
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bool "1GiB"
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config MAXPHYSMEM_2GB
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depends on 64BIT
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bool "2GiB"
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config MAXPHYSMEM_128GB
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depends on 64BIT && CMODEL_MEDANY
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bool "128GiB"
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endchoice
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config SMP
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bool "Symmetric Multi-Processing"
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help
@@ -392,12 +363,25 @@ source "kernel/Kconfig.hz"
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config RISCV_SBI_V01
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bool "SBI v0.1 support"
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default y
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depends on RISCV_SBI
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help
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This config allows kernel to use SBI v0.1 APIs. This will be
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deprecated in future once legacy M-mode software are no longer in use.
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config RISCV_BOOT_SPINWAIT
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bool "Spinwait booting method"
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depends on SMP
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default y
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help
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This enables support for booting Linux via spinwait method. In the
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spinwait method, all cores randomly jump to Linux. One of the cores
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gets chosen via lottery and all other keep spinning on a percpu
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variable. This method cannot support CPU hotplug and sparse hartid
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scheme. It should be only enabled for M-mode Linux or platforms relying
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on older firmware without SBI HSM extension. All other platforms should
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rely on ordered booting via SBI HSM extension which gets chosen
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dynamically at runtime if the firmware supports it.
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config KEXEC
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bool "Kexec system call"
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select KEXEC_CORE

‎arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts‎

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@@ -39,6 +39,11 @@
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clock-frequency = <RTCCLK_FREQ>;
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clock-output-names = "rtcclk";
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};
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gpio-poweroff {
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compatible = "gpio-poweroff";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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};
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};
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&uart0 {

‎arch/riscv/configs/nommu_k210_defconfig‎

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@@ -29,7 +29,6 @@ CONFIG_EMBEDDED=y
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CONFIG_SLOB=y
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# CONFIG_MMU is not set
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CONFIG_SOC_CANAAN=y
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CONFIG_MAXPHYSMEM_2GB=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=2
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CONFIG_CMDLINE="earlycon console=ttySIF0"

‎arch/riscv/configs/nommu_k210_sdcard_defconfig‎

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@@ -21,7 +21,6 @@ CONFIG_EMBEDDED=y
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CONFIG_SLOB=y
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# CONFIG_MMU is not set
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CONFIG_SOC_CANAAN=y
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CONFIG_MAXPHYSMEM_2GB=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=2
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CONFIG_CMDLINE="earlycon console=ttySIF0 rootdelay=2 root=/dev/mmcblk0p1 ro"

‎arch/riscv/configs/nommu_virt_defconfig‎

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@@ -24,10 +24,8 @@ CONFIG_EXPERT=y
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# CONFIG_VM_EVENT_COUNTERS is not set
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# CONFIG_COMPAT_BRK is not set
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CONFIG_SLOB=y
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# CONFIG_SLAB_MERGE_DEFAULT is not set
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# CONFIG_MMU is not set
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CONFIG_SOC_VIRT=y
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CONFIG_MAXPHYSMEM_2GB=y
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CONFIG_SMP=y
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CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0"
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CONFIG_CMDLINE_FORCE=y

‎arch/riscv/include/asm/cpu_ops.h‎

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@@ -40,7 +40,5 @@ struct cpu_operations {
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extern const struct cpu_operations *cpu_ops[NR_CPUS];
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void __init cpu_set_ops(int cpu);
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void cpu_update_secondary_bootdata(unsigned int cpuid,
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struct task_struct *tidle);
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#endif /* ifndef __ASM_CPU_OPS_H */

‎arch/riscv/include/asm/cpu_ops_sbi.h‎

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@@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021 by Rivos Inc.
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*/
5+
#ifndef __ASM_CPU_OPS_SBI_H
6+
#define __ASM_CPU_OPS_SBI_H
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8+
#ifndef __ASSEMBLY__
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#include <linux/init.h>
10+
#include <linux/sched.h>
11+
#include <linux/threads.h>
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13+
/**
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* struct sbi_hart_boot_data - Hart specific boot used during booting and
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* cpu hotplug.
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* @task_ptr: A pointer to the hart specific tp
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* @stack_ptr: A pointer to the hart specific sp
18+
*/
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struct sbi_hart_boot_data {
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void *task_ptr;
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void *stack_ptr;
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};
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#endif
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25+
#endif /* ifndef __ASM_CPU_OPS_SBI_H */

‎arch/riscv/include/asm/csr.h‎

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@@ -40,14 +40,13 @@
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#ifndef CONFIG_64BIT
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#define SATP_PPN _AC(0x003FFFFF, UL)
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#define SATP_MODE_32 _AC(0x80000000, UL)
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#define SATP_MODE SATP_MODE_32
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#define SATP_ASID_BITS 9
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#define SATP_ASID_SHIFT 22
4645
#define SATP_ASID_MASK _AC(0x1FF, UL)
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#else
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#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
4948
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
50-
#define SATP_MODE SATP_MODE_39
49+
#define SATP_MODE_48 _AC(0x9000000000000000, UL)
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#define SATP_ASID_BITS 16
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#define SATP_ASID_SHIFT 44
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#define SATP_ASID_MASK _AC(0xFFFF, UL)

‎arch/riscv/include/asm/fixmap.h‎

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@@ -24,6 +24,7 @@ enum fixed_addresses {
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FIX_HOLE,
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FIX_PTE,
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FIX_PMD,
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FIX_PUD,
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FIX_TEXT_POKE1,
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FIX_TEXT_POKE0,
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FIX_EARLYCON_MEM_BASE,

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